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參數(shù)資料
| 型號： | DAC8501E2K5 |
| 英文描述： | Low-Power, Rail-to-Rail Output, 16-Bit Serial Input DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 低功耗，軌至軌輸出，16位串行輸入數(shù)字至模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 321K |
| 代理商： | DAC8501E2K5 |
DAC8501
SBAS212A
11
www.ti.com
TYPICAL CHARACTERISTICS: V
DD
= +2.7V
(Cont.)
At T
A
= +25
°
C, and +V
DD
= +2.7V, unless otherwise noted.
THEORY OF OPERATION
DAC SECTION
The architecture consists of a string DAC followed by an
output buffer amplifier. Figure 1 shows a block diagram of the
DAC architecture.
The input coding to the DAC8501 is straight binary, so the
ideal output voltage is given by:
V
V
D
OUT
REF
=
65536
where D = decimal equivalent of the binary code that is
loaded to the DAC register; it can range from 0 to 65535.
FIGURE 1. DAC8501 Architecture.
FIGURE 2. Resistor String.
RESISTOR STRING
The resistor string section is shown in Figure 2, it is simply a
string of resistors, each of value R. The code loaded into the
DAC register determines at which node on the string the voltage
is tapped off to be fed into the output amplifier by closing one
of the switches connecting the string to the amplifier. It is
ensured monotonic because it is a string of resistors.
DAC Register
REF (+)
Resistor String
REF(
–
)
Output
Amplifier
GND
V
DD
V
OUT
V
FB
To Output
Amplifier
R
R
R
R
R
CODE CHANGE GLITCH
Time (2
μ
s/div)
V
O
(
Glitch Waveform (20mV/div)
(1)
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