參數(shù)資料
型號： DAC8532IDGKR
英文描述： BASE, BLACK;
中文描述： 雙通道，低功耗，16位，串行輸入數(shù)字到模擬轉(zhuǎn)換器
文件頁數(shù)： 3/19頁
文件大?。?/td> 402K
代理商： DAC8532IDGKR
3
DAC8532
SBAS246A
www.ti.com
REFERENCE INPUT
Reference Current
V
REF
= V
DD
= +5V
V
REF
= V
DD
= +3V
67
40
90
54
V
DD
μ
A
μ
A
V
k
Reference Input Range
Reference Input Impedance
0
75
LOGIC INPUTS
(2)
Input Current
V
IN
L, Input LOW Voltage
V
IN
L, Input LOW Voltage
V
IN
H, Input HIGH Voltage
V
H, Input HIGH Voltage
Pin Capacitance
±
1
0.8
0.6
μ
A
V
V
V
V
pF
V
DD
= +5V
V
DD
= +3V
V
DD
= +5V
V
DD
= +3V
2.4
2.1
3
POWER REQUIREMENTS
V
DD
I
DD
(normal mode)
V
DD
= +3.6V to +5.5V
V
DD
= +2.7V to +3.6V
I
DD
(all power-down modes)
V
DD
= +3.6V to +5.5V
V
DD
= +2.7V to +3.6V
POWER EFFICIENCY
I
OUT
/I
DD
TEMPERATURE RANGE
Specified Performance
2.7
5.5
V
DAC Active and Excluding Load Current
V
IH
= V
DD
and V
IL
= GND
V
IH
= V
DD
and V
IL
= GND
500
450
800
750
μ
A
μ
A
V
IH
= V
DD
and V
IL
= GND
V
IH
= V
DD
and V
IL
= GND
0.2
0.05
1
1
μ
A
μ
A
I
LOAD
= 2mA, V
DD
= +5V
89
%
–
40
+105
°
C
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ELECTRICAL CHARACTERISTICS
(Cont.)
V
DD
= +2.7V to +5.5V.
–
40
°
C to +105
°
C, unless otherwise specified.
DAC8532
NOTES: (1) Linearity calculated using a reduced code range of 485 to 64714; output unloaded. (2) Ensured by design and characterization, not production tested.
PIN
NAME
DESCRIPTION
1
2
3
4
5
V
DD
V
REF
V
OUT
B
V
OUT
A
SYNC
Power supply input, +2.7V to +5.5V.
Reference voltage input.
Analog output voltage from DAC B.
Analog output voltage from DAC A.
Level triggered SYNC input (active LOW). This is the
frame synchronization signal for the input data.
When SYNC goes LOW, it enables the input shift
register and data is transferred on the falling edge of
SCLK. The action specified by the 8-bit control byte
and 16-bit data word is executed following the 24th
falling SCLK clock edge (unless SYNC is taken
HIGH before this edge in which case the rising edge
of SYNC acts as an interrupt and the write sequence
is ignored by the DAC8532).
Serial Clock Input. Data can be transferred at rates
up to 30 MHz at 5V.
Serial Data Input. Data is clocked into the 24-bit
input shift register on each falling edge of the serial
clock input.
Ground reference point for all circuitry on the part.
6
SCLK
7
D
IN
8
GND
PIN DESCRIPTIONS
PIN CONFIGURATION
Top View
MSOP-8
V
DD
V
REF
V
OUT
B
V
OUT
A
GND
D
IN
SCLK
SYNC
1
2
3
4
8
7
6
5
DAC8532
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