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參數(shù)資料
| 型號： | DAC8551IDRBT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 16-BIT, ULTRA-LOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 16位，超低毛刺電壓輸出數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 16/22頁 |
| 文件大小： | 1740K |
| 代理商： | DAC8551IDRBT |
www.ti.com
POWER-DOWN MODES
The DAC8551 supports four separate modes of
operation. These modes are programmable by setting
two bits (PD1 and PD0) in the control register.
Table 1
shows how the state of the bits corresponds
to the mode of operation of the device.
80C51/80L51
(1)
P3.3
TXD
RXD
(1)
SYNC
SCLK
D
IN
NOTE: (1) Additional pins omitted for clarity.
DAC8551
DAC8551 to Microwire Interface
SYNC
SCLK
D
IN
Microwire
TM
CS
SK
SO
DAC8551
(1)
NOTE: (1) Additional pins omitted for clarity.
DAC8551 to 68HC11 Interface
Amplifier
PowerDown
Circuitry
Resistor
Network
V
OUT
V
FB
Resistor
String DAC
MICROPROCESSOR INTERFACING
DAC8551 TO 8051 Interface
DAC8551
SLAS429A–APRIL 2005–REVISED JULY 2005
The setup for the interface is as follows: TXD of the
8051 drives SCLK of the DAC8551, while RXD drives
the serial data line of the device. The SYNC signal is
derived from a bit-programmable pin on the port of
the 8051. In this case, port line P3.3 is used. When
data is to be transmitted to the DAC8551, P3.3 is
taken LOW. The 8051 transmits data in 8-bit bytes;
thus, only eight falling clock edges occur in the
transmit cycle. To load data to the DAC, P3.3 is left
LOW after the first eight bits are transmitted, then a
second write cycle is initiated to transmit the second
byte of data. P3.3 is taken HIGH following the
completion of the third write cycle. The 8051 outputs
the serial data in a format which has the LSB first.
The DAC8551 requires its data with the MSB as the
first bit received. The 8051 transmit routine must
therefore take this into account, and
mirror
the data
as needed.
Table 1. Modes of Operation for the DAC8551
PD1
(DB17)
0
–
0
1
1
PD0
(DB16)
0
–
1
0
1
OPERATING MODE
Normal Operation
Power-down modes
Output typically 1 k
to GND
Output typically 100 k
to GND
High-Z
When both bits are set to 0, the device works
normally with its typical current consumption of 200
μA at 5 V. However, for the three power-down
modes, the supply current falls to 200 nA at 5 V (50
nA at 3 V). Not only does the supply current fall, but
the output stage is also internally switched from the
output of the amplifier to a resistor network of known
values. This has the advantage that the output
impedance of the device is known while it is in
power-down mode. There are three different options.
The output is connected internally to GND through a
1-k
resistor,
a
100-k
open-circuited (High-Z). The output stage is illustrated
in
Figure 51
.
Figure 52. DAC8551 to 80C51/80L51 Interface
resistor,
or
it
is
left
Figure 53
shows an interface between the DAC8551
and any Microwire compatible device. Serial data is
shifted out on the falling edge of the serial clock and
is clocked into the DAC8551 on the rising edge of the
SK signal.
All
power-down mode is activated. However, the con-
tents of the DAC register are unaffected when in
power down. The time to exit power-down is typically
2.5 μs for V
= 5 V, and 5 μs for V
= 3 V. See the
Typical Characteristics for more information.
analog
circuitry
is
shut
down
when
the
Figure 53. DAC8551 to Microwire Interface
Figure 54
shows a serial interface between the
DAC8551 and the 68HC11 microcontroller. SCK of
the 68HC11 drives the SCLK of the DAC8551, while
the MOSI output drives the serial data line of the
DAC. The SYNC signal is derived from a port line
(PC7), similar to the 8051 diagram.
Figure 51. Output Stage During Power Down
See
Figure 52
for a serial interface between the
DAC8551 and a typical 8051-type microcontroller.
16
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