參數資料
| 型號： | DAC8562FPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 13/16頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT PARALLEL 5V 20-DIP |
| 產品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 18 |
| 設置時間： | 16µs |
| 位數： | 12 |
| 數據接口： | 并聯 |
| 轉換器數目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 30mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 供應商設備封裝： | 20-PDIP |
| 包裝： | 管件 |
| 輸出數目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 62.5k |
| 產品目錄頁面： | 786 (CN2011-ZH PDF) |
DAC8562
REV. A
–6–
As with any analog system, it is recommended that the
DAC8562 power supply be bypassed on the same PC card that
contains the chip. Figure 10 shows the power supply rejection
versus frequency performance. This should be taken into ac-
count when using higher frequency switched-mode power sup-
plies with ripple frequencies of 100 kHz and higher.
One advantage of the rail-to-rail output amplifier used in the
DAC8562 is the wide range of usable supply voltage. The part is
fully specified and tested over temperature for operation from
+4.75 V to +5.25 V. If reduced linearity and source current ca-
pability near full scale can be tolerated, operation of the
DAC8562 is possible down to +4.3 volts. The minimum operat-
ing supply voltage versus load current plot, in Figure 11, pro-
vides information for operation below VDD = +4.75 V.
TIMING AND CONTROL
The DAC8562 has a 12-bit DAC register that simplifies inter-
face to a 12-bit (or wider) data bus. The latch is controlled by
the Chip Enable (CE) input. If the application does not involve
a data bus, wiring CE low allows direct operation of the DAC.
The data latch is level triggered and acquires data from the data
bus during the time period when CE is low. When CE goes
high, the data is latched into the register and held until CE re-
turns low. The minimum time required for the data to be
present on the bus before CE returns high is called the data
setup time (tDS) as seen in Figure 2. The data hold time (tDH) is
the amount of time that the data has to remain on the bus after
CE
goes high. The high speed timing offered by the DAC8562
provides for direct interface with no wait states in all but the
fastest microprocessors.
Typical Performance Characteristics
5
2
0
10
100
100k
10k
1k
1
3
4
LOAD RESISTANCE –
OUTPUT
VOLTAGE
–
Volts
RL TIED TO AGND
D = FFFH
RL TIED TO AGND
DATA = FFFH
VDD = +5V
TA = +25°C
RL TIED TO +5V
DATA = 000H
Figure 5. Output Swing vs. Load
TIME = 1ms/DIV
10
90
100
0%
50mV
1ms
TA = 25°C
NBW = 630kHz
OUTPUT
NOISE
VOLTAGE
–
500V/DIV
Figure 8. Broadband Noise
1
10
1000
100
1
0.01
0.1
10
OUTPUT SINK CURRENT – A
OUTPUT
PULLDOWN
VOLTAGE
–
mV
VDD = +5V
DATA = 000H
TA = +85°C
TA = –40°C
TA = +25°C
Figure 6. Pull-Down Voltage vs.
Output Sink Current Capability
5
0
5
1
0
3
2
4
3
24
1
LOGIC VOLTAGE VALUE – Volts
SUPPLY
CURRENT
–
mA
VDD = +5V
TA = +25°C
Figure 9. Supply Current vs. Logic
Input Voltage
80
–100
–60
–80
1
–20
–40
0
20
40
60
3
2
OUTPUT VOLTAGE – Volts
OUTPUT
CURRENT
–
mA
POS0
CURRENT0
LIMIT0
NEG
CURRENT
LIMIT
DATA = 800H
RL TIED TO +2V
Figure 7. IOUT vs. VOUT
100
0
10
100
100k
10k
1k
60
80
20
40
POWER
SUPPLY
REJECTION
–
dB
FREQUENCY – Hz
VDD = +5V ±200mV AC
TA = +25°C
DATA = FFFH
Figure 10. Power Supply Rejection
vs. Frequency
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