參數(shù)資料
型號: DAC8562FS-REEL
廠商: Analog Devices Inc
文件頁數(shù): 7/16頁
文件大?。?/td> 0K
描述: IC DAC 12BIT PARALLEL 5V 20-SOIC
產(chǎn)品培訓模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 1,000
設置時間: 16µs
位數(shù): 12
數(shù)據(jù)接口: 并聯(lián)
轉換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 30mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應商設備封裝: 20-SOIC W
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): 62.5k
DAC8562
REV. A
–15–
DAC8562 – M68HC11 Interface Program Source Code
*
* DAC8562 to M68HC11 Interface Assembly Program
* Adolfo A. Garcia
* September 14, 1992
*
* M68HC11 Register definitions
*
PORTB
EQU
$1004
PORTC
EQU
$1003
Port C control register
*
“0,0,0,0;0,CLR/,CE/,MSB-LSB/”
DDRC
EQU
$1007
Port C data direction
*
* RAM variables:
MSBS are encoded from 0 (Hex) to F (Hex)
*
LSBS are encoded from 00 (Hex) to F (Hex)
*
DAC requires two 8-bit loads
*
MSBS
EQU
$00
Hi-byte: “0,0,0,0;MSB,DB10,DB9,DB8”
LSBS
EQU
$01
Lo-byte: “DB7,DB6,DB5,DB4;DB3,DB2,
DB1,DB0”
*
* Main Program
*
ORG
$C000
Start of user’s RAM in EVB
INIT
LDS
#$CFFF
Top of C page RAM
*
* Initialize Port C Outputs
*
LDAA
#$07
0,0,0,0;0,1,1,1
STAA
DDRC
CLR/,CE/, and MSB-LSB/ are now enabled
as outputs
LDAA
#$06
0,0.0,0;0,1,1,0
*
CLR/-Hi, CE/-Hi, MSB-LSB/-Lo
STAA
PORTC
Initialize Port C Outputs
*
* Call update subroutine
*
BSR
UPDATE
Xfer 2 8-bit words to DAC8562
JMP
$E000
Restart BUFFALO
*
* Subroutine UPDATE
*
UPDATE
PSHX
Save registers X, Y, and A
PSHY
PSHA
*
* Enter contents of the Hi-byte input register
*
LDAA
#$0A
0,0,0,0;1,0,1,0
STAA
MSBS
MSBS are set to 0A (Hex)
*
* Enter Contents of’ Lo-byte input register
*
LDAA
#$AA
1,0,1,0;1,0,1,0
STAA
LSBS
LSBS are set to AA (Hex)
*
LDX
#MSBS
Stack pointer at 1st byte to send via Port B
LDY
#$1000
Stack pointer at on-chip registers
*
* Clear DAC output to zero
*
BCLR
PORTC,Y $04
Assert CLR/
BSET
PORTC,Y $04
De-assert CLR/
*
* Loading input buffer latches
*
BSET
PORTC,Y $01
Set hi-byte register load
TFRLP
LDAA
0,X
Get a byte to transfer via Port B
STAA
PORTB
Write data to input register
INX
Increment counter to next byte for transfer
CPX
#LSBS+1
Are we done yet ?
BEQ
DUMP
If yes, update DAC output
BCLR
PORTC,Y $01
Latch hi-byte register and set lo-byte register
load
BRA
TFRLP
*
DAC8562–M68HC11 Interface Program Source Code (Continued)
* Update DAC output with contents of input registers
*
DUMP
BCLR
PORTC,Y $02
Assert CE/
BSET
PORTC,Y $02
Latch DAC register
*
PULA
When done, restore registers X, Y & A
PULY
PULX
RTS
** Return to Main Program **
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