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參數(shù)資料
| 型號： | DAC8562FS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | CONN TERM BLOCK 2POS 3.5MM PCB |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 16 us SETTLING TIME, 12-BIT DAC, PDSO20 |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 636K |
| 代理商： | DAC8562FS |
DAC8562–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Condition
Min
Typ
Max
Units
STATIC PERFORMANCE
Resolution
Relative Accuracy
N
INL
Note 2
E Grade
F Grade
No Missing Codes
Data = 000
Data - FFF
H
E Grade
F Grade
Notes 3, 4
12
–1/2
–1
–1
Bits
LSB
LSB
LSB
LSB
±
1/4
±
3/4
±
3/4
+1/2
+1/2
+1
+1
+3
Differential Nonlinearity
Zero-Scale Error
Full-Scale Voltage
DNL
V
ZSE
V
FS
4.087
4.079
4.095
4.095
±
16
4.103
4.111
V
V
ppm/
°
C
Full-Scale Tempco
TCV
FS
ANALOG OUTPUT
Output Current
Load Regulation at Half Scale
Capacitive Load
I
OUT
LD
REG
C
L
Data = 800
H
R
L
= 402
to
∞
, Data = 800
H
No Oscillation
4
±
5
±
7
1
500
mA
LSB
pF
3
REFERENCE OUTPUT
Output Voltage
Output Source Current
Line Rejection
Load Regulation
V
REF
I
REF
LN
REJ
LD
REG
2.484
5
2.500
7
2.516
V
mA
%/V
%/mA
Note 5
0.08
0.1
I
REF
= 0 to 5 mA
LOGIC INPUTS
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance
V
IL
V
IH
I
IL
C
IL
0.8
V
V
μ
A
pF
2.4
10
10
Note 4
INTERFACE TIMING SPECIFICATIONS
1, 4
Chip Enable Pulse Width
Data Setup
Data Hold
Clear Pulse Width
t
CEW
t
DS
t
DH
t
CLRW
30
30
10
20
ns
ns
ns
ns
AC CHARACTERISTICS
4
Voltage Output Settling Time
6
Digital Feedthrough
t
S
To
±
1 LSB of Final Value
16
35
μ
s
nV sec
SUPPLY CHARACTERISTICS
Positive Supply Current
I
DD
V
IH
= 2.4 V, V
IL
= 0.8 V
V
IL
= 0 V, V
DD
= +5 V
V
IH
= 2.4 V, V
IL
= 0.8 V
V
IL
= 0 V, V
DD
= +5V
V
DD
=
±
5%
3
0.6
15
3
0.002
6
1
30
5
0.004
mA
mA
mW
mW
%/%
Power Dissipation
P
DISS
Power Supply Sensitivity
PSS
NOTES
1
All input control signals are specified with t
= t
f
= 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
2
1 LSB = 1 mV for 0 to +4.095 V output range.
3
Includes internal voltage reference error.
4
These parameters are guaranteed by design and not subject to production testing.
5
Very little sink current is available at the REFOUT pin. Use external buffer if setting up a virtual ground.
6
The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in
this 6 LSB region.
Specifications subject to change without notice.
–2–
(@ V
DD
= +5.0
6
5%, R
S
= No Load, –40
8
C
≤
T
A
≤
+85
8
C, unless otherwise noted)
REV. A
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