參數(shù)資料
型號： DAC8571IDGKR
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： SERIAL INPUT LOADING, 13 us SETTLING TIME, 16-BIT DAC, PDSO8
封裝： GREEN, PLASTIC, MSOP-8
文件頁數(shù)： 23/30頁
文件大?。?/td> 825K
代理商： DAC8571IDGKR
www.ti.com
ELECTRICAL CHARACTERISTICS
DAC8571
SLAS373A – DECEMBER 2002 – REVISED JULY 2003
V
DD = +2.7 V to +5.5 V; RL = 2 k to GND; CL = 200 pF to GND; low power mode; all specifications -40°C to 105°C (unless
otherwise noted)
DAC8571
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE (1)
Resolution
16
Bits
Relative accuracy
±0.098
% of FSR
Differential nonlinearity
Monotonic by design
±0.25
±1
LSB
Offset error
Measured at code 485, 25
°C
0.3
±1.0
mV
Measured at code 485, -40
°C...105°C
1.0
±5.0
Full-scale error
Measured at code 64714, 25
°C
0.5
±3.0
mV
Measured at code 64714, -40
°C...105°C
1.0
±5.0
Gain error
Measured at code 64714, 25
°C
1.0
±3.0
mV
Measured at code 64714, -40
°C...105°C
2.0
±5.0
Zero code error drift
All zeroes loaded to DAC register
-20
V/
°C
Gain temperature coefficient
-5
ppm of FSR/
°C
Absolute accuracy
All codes from code 485 to code 64714, 25
°C
±2.5
mV
All codes from code 485 to code 64714,
±3.5
-40
°C...105°C
OUTPUT CHARACTERISTICS(2)
Output voltage range
0
VREF
V
Output voltage settling time (full
RL = 2 k; CL < 200 pF, fast settling
8
10
s
scale)
RL = 2 k; CL = 500 pF, fast settling
12
s
RL = 2 k; CL < 200 pF, low power
13
15
s
Slew rate
RL = 2 k; CL < 200 pF, fast settling
1
V/s
RL = 2 k; CL < 200 pF, low power
0.5
Capacitive load stability
RL = ∞
470
pF
RL = 2 k
1000
pF
Digital-to-analog glitch impulse
20
nV-s
Digital feedthrough
0.5
nV-s
DC output impedance
1
Short circuit current
VDD = +5 V
50
mA
VDD = +3 V
20
mA
Power-up time
Coming out of power-down mode, VDD = +5 V
2.5
s
Coming out of power-down mode, VDD = +3 V
5
s
PSRR
0.75
mV/V
REFERENCE INPUT
VREFH input range
0
VDD
V
Reference input impedance
140
k
LOGIC INPUTS (2)
Input current
±1
A
VIN_L, Input low voltage
VDD = 2.7-5.5 V
0.3VDD
V
VIN_H0 , Input high voltage
VDD = 2.7-5.5 V
0.7VDD
V
Pin capacitance
3
pF
POWER REQUIREMENTS
VDD
2.7
5.5
V
IDD (normal operation)
DAC active, Iref included
(1)
Linearity calculated using a reduced code range of 485 to 64714. Output unloaded.
(2)
Assured by design and characterization, not production tested.
3
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