參數(shù)資料
型號: DAC8811B
廠商: Texas Instruments, Inc.
英文描述: 16-Bit, Serial Input Multiplying Digital-to-Analog Converter
中文描述: 16位串行輸入乘法數(shù)字到模擬轉(zhuǎn)換器
文件頁數(shù): 9/15頁
文件大小: 421K
代理商: DAC8811B
www.ti.com
t
(CSS)
t
(DS)
t
(DH)
t
(CH)
t
(CL)
t
(CSH)
SDI
CLK
CS
D15
D14 D13 D12
D11 D10
D9
D8
D1
D0
APPLICATION INFORMATION
Stability Circuit
For a current-to-voltage design (see Figure 20), the DAC8811 current output (I
OUT
) and the connection with the
inverting node of the op amp should be as short as possible and according to correct PCB layout design. For
each code change there is a step function. If the GBP of the op amp is limited and parasitic capacitance is
excessive at the inverting node then gain peaking is possible. Therefore, for circuit stability, a compensation
capacitor C1 (4 pF to 20 pF typ) can be added to the design, as shown in Figure 20.
+
U2
GND
U1
V
REF
V
REF
V
DD
V
DD
V
OUT
C1
I
OUT
R
FB
Positive Voltage Output Circuit
As Figure 21 illustrates, in order to generate a positive voltage output, a negative reference is input to the
DAC8811. This design is suggested instead of using an inverting amp to invert the output due to tolerance errors
of the resistor. For a negative reference, V
OUT
and GND of the reference are level-shifted to a virtual ground and
a -2.5 V input to the DAC8811 with an op amp.
DAC8811
SLAS411A–NOVEMBER 2004–REVISED DECEMBER 2004
THEORY OF OPERATION (continued)
Figure 19. DAC8811 Timing Diagram
Table 2. Control Logic Truth Table
(1)
CLK
X
+
X
X
CS
H
L
H
+
Serial Shift Register
No effect
Shift register data advanced one bit
No effect
Shift register data transferred to DAC register
DAC Register
Latched
Latched
Latched
New data loaded from serial register
(1)
+ Positive logic transition; X = Don't care
Table 3. Serial Input Register Data Format, Data Loaded MSB First
B15
(MSB)
D15
B0
Bit
Data
B14
D14
B13
D13
B12
D12
B11
D11
B10
D10
B9
D9
B8
D8
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
(LSB)
D0
Figure 20. Gain Peaking Prevention Circuit With Compensation Capacitor
9
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