參數(shù)資料
型號: DAC902U
元件分類: DAC
英文描述: PARALLEL, WORD INPUT LOADING, 0.03 us SETTLING TIME, 12-BIT DAC, PDSO28
封裝: SO-28
文件頁數(shù): 11/16頁
文件大小: 216K
代理商: DAC902U
4
DAC902
PIN
DESIGNATOR
DESCRIPTION
1
Bit 1
Data Bit 1 (D11), MSB
2
Bit 2
Data Bit 2 (D10)
3
Bit 3
Data Bit 3 (D9)
4
Bit 4
Data Bit 4 (D8)
5
Bit 5
Data Bit 5 (D7)
6
Bit 6
Data Bit 6 (D6)
7
Bit 7
Data Bit 7 (D5)
8
Bit 8
Data Bit 8 (D4)
9
Bit 9
Data Bit 9 (D3)
10
Bit 10
Data Bit 10 (D2)
11
Bit 11
Data Bit 11 (D1)
12
Bit 12
Data Bit 12 (D0), LSB
13
NC
No Connection
14
NC
No Connection
15
PD
Power Down, Control Input; Active
High. Contains internal pull-down circuit;
may be left unconnected if not used.
16
INT/EXT
Reference Select Pin; Internal ( = 0) or
External ( = 1) Reference Operation.
17
REFIN
Reference Input/Ouput. See Applica-
tions section for further details.
18
FSA
Full-Scale Output Adjust
19
BW
Bandwidth/Noise Reduction Pin:
Bypass with 0.1
F to +V
A for Optimum
Performance.
20
AGND
Analog Ground
21
IOUT
Complementary DAC Current Output
22
IOUT
DAC Current Output
23
BYP
Bypass Node: Use 0.1
F to AGND
24
+VA
Analog Supply Voltage, 2.7V to 5.5V
25
NC
No Connection
26
DGND
Digital Ground
27
+VD
Digital Supply Voltage, 2.7V to 5.5V
28
CLK
Clock Input
PIN DESCRIPTIONS
PIN CONFIGURATION
Top View
SOIC, TSSOP
TYPICAL CONNECTION CIRCUIT
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
NC
CLK
+V
D
DGND
NC
+V
A
BYP
I
OUT
I
OUT
AGND
BW
FSA
REF
IN
INT/EXT
PD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DAC902
Current
Sources
LSB
Switches
Segmented
MSB
Switches
+1.24V Ref.
Latches
12-Bit Data Input
D11.......D0
DAC902
FSA
BW
+V
D
+V
A
R
SET
AGND
CLK
DGND
REF
IN
0.1
F
INT/EXT
I
OUT
I
OUT
BYP
PD
20pF
50
50
20pF
1:1
0.1
F
0.1
F
+5V
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