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參數(shù)資料
| 型號： | DATASHEET |
| 英文描述： | ST10F168 - 16-BIT MCU - 8KB RAM - 256KB FLASH MEMORY - 111 I/O - 1 CAN 2.0B INTERFACE |
| 中文描述： | ST10F168 - 16位MCU - 8KB的內(nèi)存- 256KB的快閃記憶體- 111的I / O - 1 CAN 2.0B總線接口 |
| 文件頁數(shù)： | 52/74頁 |
| 文件大?。?/td> | 897K |
| 代理商： | DATASHEET |
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ST10F168
52/74
Figure 15 :
Supply / idle current as a function of operation frequency
20.4 - A/D Converter Characteristics
V
DD
= 5V ±10%, V
SS
= 0V, 4.0V
≤
V
AREF
≤
V
DD
+ 0.1V, V
SS
- 0.1V
≤
V
AGND
≤
V
SS
+ 0.2V, Q6 version :
T
A
= -40, +85°C and for Q3 version T
A
= -40°C, +125°C, unless otherwise specified
Notes: 1. V
AIN
may exceed V
AGND
or V
AREF
up to the absolute maximum ratings. However, the conversion result in these cases will be
X000h or X3FFh, respectively.
2. During the t
S
sample time the input capacitance C
ain
can be charged/discharged by the external source. The internal resistance of
the analog source must allow the capacitance to reach its final voltage level within the t
S
sample time. After the end of the t
S
sample
time, changes of the analog input voltage have no effect on the conversion result. Values for the t
SC
sample clock depend on the
programming. Referring to the t
C
conversion time formula of chapter 13, to the table 17 of page 33 and to the table below:
t
S
min = 2 t
SC
min = 2 t
CC
min = 2 x 24 x TCL = 48 TCL
t
S
max = 2 t
SC
max = 2 x 8 t
CC
max = 2 x 8 x 96 TCL = 1536 TCL
TCL is defined in section 20.5.5 at page 55.
3. The conversion time formula is:
t
C
= 14 t
CC
+ t
S
+ 4 TCL (= 14 t
CC
+ 2 t
SC
+ 4 TCL)
The t
C
parameter includes the t
S
sample time, the time for determining the digital result and the time to load the result register with
the result of the conversion. Values for the t
CC
conversion clock depend on the programming. Referring to the table 17 of page 33 and
to the table below:
t
C
min = 14 t
CC
min + t
S
min + 4 TCL = 14 x 24 x TCL + 48 TCL + 4 TCL = 388 TCL
t
C
max = 14 t
CC
max + t
S
max + 4 TCL = 14 x 96 TCL + 1536 TCL + 4 TCL = 2884 TCL
4. This parameter is fixed by ADC control logic.
5. TUE is tested at V
AREF
= 5.0V, V
AGND
= 0V, V
CC
= 4.9V. It is guaranteed by design characterization for all other voltages within the
defined voltage range. The specified TUE is guaranteed only if an overload condition (see Iov specification) occurs on maximum of 2
not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10mA.
During the reset calibration sequence the maximum TUE may be
±
4 LSB.
Symbol
Parameter
Test
Conditions
Min.
Max.
Unit
V
AIN
SR Analog input voltage range
1 - 8
V
AGND
V
AREF
V
t
S
t
C
CC Sample time
2 - 4
48 TCL
1 536 TCL
CC Conversion time
3 - 4
388 TCL
2 884 TCL
TUE
CC Total unadjusted error
5
–
±
2
LSB
R
AREF
SR Internal resistance of reference voltage source
t
CC
in [ns]
6 - 7
t
S
in [ns]
2 - 7
–
(t
CC
/ 165) - 0.25
k
R
ASRC
SR Internal resistance of analog source
C
AIN
CC ADC input capacitance
–
(t
S
/ 330) - 0.25
33
k
7
–
pF
I [mA]
f
CPU
[MHz]
5
10
15
20
200
100
10
I
IDmax
I
CCmax
25
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