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參數(shù)資料
| 型號(hào)： | DC1112A |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 6/24頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DAC LTC2755-16 |
| 軟件下載： | QuikEval System |
| 設(shè)計(jì)資源： | DC1112A Design File DC1112A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuikEval™, SoftSpan™ |
| DAC 的數(shù)量： | 4 |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 設(shè)置時(shí)間： | 2µs |
| DAC 型： | 電流 |
| 工作溫度： | 0°C ~ 70°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | LTC2755-16 |
| 相關(guān)產(chǎn)品： | DC590B-ND - BOARD DEMO USB SERIAL CONTROLLER LTC2755BIUP-16#TRPBF-ND - IC DAC 16BIT CUR OUT 64-QFN LTC2755BIUP-16#PBF-ND - IC DAC 16BIT CUR OUT 64-QFN LTC2755BCUP-16#TRPBF-ND - IC DAC 16BIT CUR OUT 64-QFN LTC2755BCUP-16#PBF-ND - IC DAC 16BIT CUR OUT 64-QFN LTC2755AIUP-16#TRPBF-ND - IC DAC 16BIT CUR OUT 64-QFN LTC2755AIUP-16#PBF-ND - IC DAC 16BIT CUR OUT 64-QFN LTC2755ACUP-16#TRPBF-ND - IC DAC 16BIT CUR OUT 64-QFN LTC2755ACUP-16#PBF-ND - IC DAC 16BIT CUR OUT 64-QFN |
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LTC2755
14
2755f
Output Ranges
The LTC2755 is a quad current-output, parallel-input
precision multiplying DAC with selectable output ranges.
Rangescaneitherbeprogrammedinsoftwareformaximum
exibility, or hardwired through pin-strapping for greatest
ease of use. Two unipolar ranges are available (0V to 5V
and 0V to 10V), and four bipolar ranges (±2.5V, ±5V, ±10V
and –2.5V to 7.5V). These ranges are obtained when an
external precision 5V reference is used. When a reference
voltage of 2V is used, the ranges become: 0V to 2V, 0V
to 4V, ±1V, ±2V, ±4V and –1V to 3V. The output ranges are
linearly scaled for references other than 2V and 5V.
Digital Section
The LTC2755 has 4 internal registers for each DAC, a total
of 16 registers (see Block Diagram). Each DAC channel
has two sets of double-buffered registers—one set for
the data, and one set for the span (output range) of the
DAC. The double-buffered feature provides the capability
to simultaneously update the span and code, which al-
lows smooth voltage transitions when changing output
ranges. It also permits the simultaneous updating of
multiple DACs.
Each set of double-buffered registers comprises an input
register and a DAC register. The input registers are holding
buffers—when data is loaded into an input register via a
write operation, the DAC outputs are not affected.
The contents of a DAC register, on the other hand, di-
rectly control the DAC output voltage or output range.
The contents of the DAC registers are changed by copying
the contents of an input register into its associated DAC
register via an update operation.
Write and Update Operations
The data input register of the addressed DAC is loaded
directly from a 16-bit microprocessor bus by holding the
D/S pin low and pulsing the WR pin low (write operation).
The DAC register is loaded by pulsing the UPD pin high
(update operation), which copies the data held in the input
register into the DAC register. Note that updates always
include both data and span; but the DAC register values
will not change unless the associated input register values
have previously been changed via a write operation.
Loading the span input register is accomplished similarly,
holding the D/S pin high and pulsing the WR pin low. The
span and data register structures are the same except for
the number of parallel bits—the span registers have 3 bits,
while the data registers have 12, 14 or 16 bits.
To make both registers transparent for owthrough
mode, tie WR low and UPD high. However, this defeats
the deglitcher operation and output glitch impulse may
increase. The deglitcher is activated on the rising edge
of the UPD pin.
The interface also allows the use of the input and DAC
registers in a master-slave, or edge-triggered, congura-
tion. This mode of operation occurs when WR and UPD
are tied together and driven by a single clock signal. The
data bits are loaded into the input register on the falling
edge of the clock and then loaded into the DAC register
on the rising edge.
It is possible to control both data and span on one 16-bit
wide data bus by allowing span pins S2 to S0 to share
bus lines with the data LSBs (D2 to D0). No write or read
operation includes both span and data, so there cannot
be a conict.
The asynchronous clear pin resets all DACs to 0V in any
output range. CLR resets all data registers, while leaving
the span registers undisturbed.
OPERATION
Figure 1. Using MSPAN to Congure the LTC2755 for Single-Span
Operation (±10V Range).
LTC2755-16
MSPAN
S2
S1
S0
D/S
2755 F01
WR UPD READ A2
DAC ADDRESS
A1 A0
DATA
I/O
VDD
DAC A
±10V
DAC B
DAC C
DAC D
16
–
+
–
+
–
+
–
+
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