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參數(shù)資料
| 型號： | DC1562A-B |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL LTC6991 |
| 設(shè)計資源： | DC1562A Design Files DC1562A Schematic |
| 特色產(chǎn)品： | TimerBlox? |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TimerBlox® |
| 主要目的： | 計時，時鐘振蕩器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | LTC6991 |
| 主要屬性： | 1Hz 固定頻率 |
| 次要屬性： | 2.25 V ~ 5.5 V 電源 |
| 已供物品： | 板 |
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LTC6991
14
6991fb
APPLICATIONS INFORMATION
Basic Operation
The simplest and most accurate method to program the
LTC6991 is to use a single resistor, RSET, between the SET
and GND pins. The design procedure is a 3-step process.
First select the POL bit setting and NDIVvalue,thencalculate
the value for the RSET resistor.
Alternatively, Linear Technology offers the easy to use
TimerBlox Designer tool to quickly design any LTC6991
based circuit. Download the free TimerBlox Designer
software at www.linear.com/timerblox.
Step 1: Select the POL Bit Setting
The LTC6991 can operate in normal (active-high) or inverted
(active-low) modes, depending on the setting of the POL
bit. The best choice depends on the the application.
Step 2: Select the NDIV Frequency Divider Value
As explained earlier, the voltage on the DIV pin sets the
DIVCODE which determines both the POL bit and the NDIV
value. For a given output clock period, NDIV should be
selected to be within the following range.
tOUT
16.384ms
≤ NDIV ≤
tOUT
1.024ms
(1)
To minimize supply current, choose the lowest NDIV value
(generally recommended). Alternatively, use Table 1
as a guide to select the best NDIV value for the given
application.
With POL already chosen, this completes the selection of
DIVCODE. Use Table 1 to select the proper resistor divider
or VDIV/V+ ratio to apply to the DIV pin.
Step 3: Calculate and Select RSET
The final step is to calculate the correct value for RSET
using the following equation.
RSET =
50k
1.024ms
tOUT
NDIV
(2)
Select the standard resistor value closest to the calculated
value.
Example: Design a 1Hz oscillator with minimum power
consumption and active-high reset input.
Step 1: Select the POL Bit Setting
For noninverted (active-high) functionality, choose
POL = 0.
Step 2: Select the NDIV Frequency Divider Value
Choose an NDIV value that meets the requirements of
Equation (1), using tOUT = 1000ms:
61.04 ≤ NDIV ≤ 976.6
Potential settings for NDIV include 64 and 512. NDIV = 64
is the best choice, as it minimizes supply current by us-
ing a large RSET resistor. POL = 0 and NDIV = 64 requires
DIVCODE = 2. Using Table 1, choose R1 = 976k and
R2 = 182k values to program DIVCODE = 2.
Step 3: Select RSET
Calculate the correct value for RSET using Equation (2).
RSET =
50k
1.024ms
1000ms
64
= 763k
Since 763k is not available as a standard 1% resistor,
substitute 768k if a –0.7% frequency shift is acceptable.
Otherwise, select a parallel or series pair of resistors such
as 576k + 187k to attain a more precise resistance.
The completed design is shown in Figure 11.
DIVCODE = 2
6991 F11
LTC6991
RST
GND
SET
RST
OUT
V+
DIV
R1
976k
R2
182k
RSET
763k
2.25V TO 5.5V
Figure 11. 1Hz Oscillator
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