ADC TIMING CHARACTERISTICS The l denotes the specifications which apply over the " />
參數(shù)資料
型號(hào)： DC1813A-A
廠商： Linear Technology
文件頁(yè)數(shù)： 20/24頁(yè)
文件大?。?/td> 0K
描述： BOARD SAR ADC LTC2370-16
軟件下載： QuikEval II System
設(shè)計(jì)資源： DC1813A Design File
DC1813A Schematic
標(biāo)準(zhǔn)包裝： 1
系列： QuikEval-II™
ADC 的數(shù)量： 1
位數(shù)： 16
采樣率（每秒）： 2M
數(shù)據(jù)接口： 串行，SPI?
輸入范圍： 0 ~ VREF
在以下條件下的電源（標(biāo)準(zhǔn)）： 19mW @ 2MSPS
工作溫度： 0°C ~ 70°C
已用 IC / 零件： LTC2370-16
已供物品： 板
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LTC2370-16
5
237016fa
ADC TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
tSCKL
SCK Low Time
l
4
ns
tSSDISCK
SDI Setup Time From SCK
↑
(Note 11)
l
4
ns
tHSDISCK
SDI Hold Time From SCK
↑
(Note 11)
l
1
ns
tSCKCH
SCK Period in Chain Mode
tSCKCH = tSSDISCK + tDSDO (Note 11)
l
13.5
ns
tDSDO
SDO Data Valid Delay from SCK
↑
CL = 20pF (Note 11)
l
9.5
ns
tHSDO
SDO Data Remains Valid Delay from SCK
↑
CL = 20pF (Note 10)
l
1
ns
tDSDOBUSYL SDO Data Valid Delay from BUSY↓
CL = 20pF (Note 10)
l
5
ns
tEN
Bus Enable Time After RDL
↓
(Note 11)
l
16
ns
tDIS
Bus Relinquish Time After RDL
↑
(Note 11)
l
13
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may effect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above REFor
OVDD, they will be clamped by internal diodes. This product can handle
input currents up to 100mA below ground or above REF or OVDD without
latch-up.
Note 4: VDD = 2.5V, OVDD = 2.5V, REF = 5V, fSMPL = 2MHz.
Note 5: Recommended operating conditions.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Zero-scale error is the offset voltage measured from 0.5LSB
when the output code flickers between 0000 0000 0000 0000 and
0000 0000 0000 0001. Full-scale error is the deviation of the last code
transition from ideal and includes the effect of offset error.
Note 8: All specifications in dB are referred to a full-scale 5V input with a
5V reference voltage.
Note 9: fSMPL = 2MHz, IREF varies proportionately with sample rate.
Note 10: Guaranteed by design, not subject to test.
Note 11: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
and OVDD = 5.25V.
Note 12: tSCK of 10ns maximum allows a shift clock frequency up to
100MHz for rising capture.
Figure 1. Voltage Levels for Timing Specifications
0.8*OVDD
0.2*OVDD
50%
237016 F01
0.2*OVDD
0.8*OVDD
0.2*OVDD
0.8*OVDD
tDELAY
tWIDTH
tDELAY
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DC1813A-C 功能描述:BOARD SAR ADC LTC2367-16 RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:QuikEval-II™ 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件
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