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參數(shù)資料
| 型號： | DC682A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD SAR ADC LTC1859 |
| 軟件下載： | QuikEval System |
| 設計資源： | DC682A Design File DC682A Schematic |
| 標準包裝： | 1 |
| 系列： | QuikEval™, SoftSpan™ |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 100k |
| 數(shù)據接口： | MICROWIRE?，串行，SPI? |
| 工作溫度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC1859 |
| 已供物品： | 板 |
| 相關產品： | LTC1859CG#PBF-ND - IC ADC 8CH 16BIT 100KSPS 28-SSOP LTC1859IG#PBF-ND - IC A/D CONV 8CH 16BIT 28-SSOP LTC1859IG#TRPBF-ND - IC A/D CONV 8CH 16BIT 28-SSOP LTC1859CG#TRPBF-ND - IC A/D CONV 8CH 16BIT 28-SSOP |
LTC1857/LTC1858/LTC1859
16
185789fa
MUX ADDRESS
The rst four bits of the input word assign the MUX
conguration for the requested conversion. For a given
channel selection, the converter will measure the voltage
between the two channels indicated by the + and – signs in
the selected row of Table 1. Note that in differential mode
(SGL/DIFF = 0) measurements are limited to four adjacent
input pairs with either polarity. In single-ended mode, all
input channels are measured with respect to COM. Both
the “+” and “–” inputs are sampled simultaneously so
common mode noise is rejected.
INPUT RANGE (UNI, GAIN)
The fth and sixth input bits (UNI, GAIN) determine the
input range for the conversion. When UNI is a logical one,
a unipolar conversion will be performed. When UNI is a
logical zero, a bipolar conversion will result. The GAIN
input bit determines the input span for the conversion.
When GAIN is a logical one, either 0V to 10V or ±10V input
spans will be selected depending on UNI. When GAIN is
a logical zero, either 0V to 5V or ±5V input spans will be
chosen. The input ranges for different UNI and GAIN inputs
are shown in Table 2.
Table 2. Input Range Selection
UNI
GAIN
INPUT RANGE
0
±5V
1
0
0V to 5V
0
1
±10V
1
0V to 10V
POWER DOWN SELECTION (NAP, SLEEP)
The last two bits of the input word (Nap and Sleep) deter-
mine the power shutdown mode of the LTC1857/LTC1858/
LTC1859. See Table 3. Nap mode is selected when Nap =
1 and Sleep = 0. The previous conversion result will be
clocked out and a conversion will occur before entering
the Nap mode. The Nap mode starts at the end of the
conversion which is indicated by the rising edge of the
BUSY signal. Nap mode lasts until the falling edge of the
2nd SCK (see Figure 9). Automatic nap will be achieved
if Nap = 1 is selected each time an input word is written
to the ADC.
Table 3. Power Down Selection
NAP
SLEEP
POWER DOWN MODE
0
Power On
10
Nap
X
1
Sleep
Sleep mode will occur when Sleep = 1 is selected,
regardless of the selection of the Nap input. The previ-
ous conversion result can be clocked out and the Sleep
mode will start on the falling edge of the last (16th) SCK.
Notice that the CONVST should stay either high or low in
sleep mode (see Figure 10). To wake up from the sleep
mode, apply a rising edge on the CONVST signal and
then apply Sleep = 0 on the next SDI word and the part
will wake up on the falling edge of the last (16th) SCK
(see Figure 11).
In Sleep mode, all bias currents are shut down and only the
power on reset circuit and leakage currents (about 10μA)
remain. Sleep mode wake-up time is dependent on the value
of the capacitor connected to the REFCOMP (Pin 16). The
wake-up time is typically 40ms with the recommended
10μF capacitor connected on the REFCOMP pin.
DYNAMIC PERFORMANCE
FFT (Fast Fourier Transform) test techniques are used to
test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion
sine wave and analyzing the digital output using an FFT
algorithm, the ADC’s spectral content can be examined
for frequencies outside the fundamental. Figure 12 shows
a typical LTC1859 FFT plot which yields a SINAD of 87dB
and THD of – 101dB.
APPLICATIONS INFORMATION
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