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參數(shù)資料
| 型號： | DC935A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 7/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DAC LTC2605 |
| 軟件下載： | QuikEval System |
| 設(shè)計資源： | DC935A Design Files DC935A Schematic |
| 標(biāo)準包裝： | 1 |
| 系列： | QuikEval™ |
| DAC 的數(shù)量： | 8 |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | I²C |
| 設(shè)置時間： | 10µs |
| DAC 型： | 電壓 |
| 工作溫度： | 0°C ~ 70°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | LTC2605 |
| 相關(guān)產(chǎn)品： | LTC2605IGN-1#TRPBF-ND - IC DAC 16BIT OCT I2C 16-SSOP LTC2605IGN#TRPBF-ND - IC DAC 16BIT OCT I2C 16-SSOP LTC2605CGN-1#TRPBF-ND - IC DAC 16BIT OCT I2C 16-SSOP LTC2605CGN#TRPBF-ND - IC DAC 16BIT OCT I2C 16-SSOP LTC2605CGN-1#PBF-ND - IC DAC 16BIT OCT I2C 16-SSOP LTC2605CGN#PBF-ND - IC DAC 16BIT OCT I2C 16-SSOP LTC2605IGN#PBF-ND - IC DAC 16BIT OCT I2C 16-SSOP LTC2605IGN-1#PBF-ND - IC DAC 16BIT OCT I2C 16-SSOP |
LTC2605/LTC2615/LTC2625
15
2605fa
Voltage Outputs
Each of the eight rail-to-rail ampliers contained in these
parts has guaranteed load regulation when sourcing or
sinking up to 15mA at 5V (7.5mA at 3V).
Load regulation is a measure of the amplier’s ability to
maintain the rated voltage accuracy over a wide range of
load conditions. The measured change in output voltage
per milliampere of forced load current change is expressed
in LSB/mA.
DC output impedance is equivalent to load regulation and
may be derived from it by simply calculating a change in
units from LSB/mA to Ohms. The amplier’s DC output
impedance is 0.020Ω when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 30Ω typical channel resistance of the output devices;
e.g., when sinking 1mA, the minimum output voltage =
30Ω 1mA = 30mV. See the graph Headroom at Rails vs
Output Current in the Typical Performance Characteristics
section.
The ampliers are stable driving capacitive loads of up
to 1000pF.
Board Layout
The excellent load regulation and DC-crosstalk performance
of these devices is achieved in part by keeping “signal”
and “power” grounds separated internally and by reducing
shared internal resistance to just 0.005Ω.
The GND pin functions both as the node to which the refer-
ence and output voltages are referred and as a return path
for power currents in the device. Because of this, careful
thought should be given to the grounding scheme and
board layout in order to ensure rated performance.
The PC board should have separate areas for the analog
and digital sections of the circuit. This keeps digital signals
away from sensitive analog signals and facilitates the
use of separate digital and analog ground planes which
have minimal capacitive and resistive interaction with
each other.
OPERATION
Digital and analog ground planes should be joined at only
one point, establishing a system star ground as close to
the device’s ground pin as possible. Ideally, the analog
ground plane should be located on the component side of
the board, and should be allowed to run under the part to
shield it from noise. Analog ground should be a continuous
and uninterrupted plane, except for necessary lead pads
and vias, with signal traces on another layer.
The GND pin of the part should be connected to analog
ground. Resistance from the GND pin to system star
ground should be as low as possible. Resistance here will
add directly to the effective DC output impedance of the
device (typically 0.020Ω), and will degrade DC crosstalk.
Note that the LTC2605/LTC2615/LTC2625 are no more
susceptible to these effects than other parts of their type;
on the contrary, they allow layout-based performance
improvements to shine rather than limiting attainable
performance with excessive internal resistance.
Rail-to-Rail Output Considerations
In any rail-to-rail voltage output device, the output is limited
to voltages within the supply range.
Since the analog outputs of the device cannot go below
ground, they may limit for the lowest codes as shown
in Figure 4b. Similarly, limiting can occur near full-scale
when the REF pin is tied to VCC. If VREF = VCC and the DAC
full-scale error (FSE) is positive, the output for the highest
codes limits at VCC as shown in Figure 4c. No full-scale
limiting can occur if VREF is less than VCC – FSE.
Offset and linearity are dened and tested over the region
of the DAC transfer function where no output limiting
can occur.
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