DE6003
3
FRMGND
V
CC
PWRLO
ANTSEL
RX/TX
V
EE
RXD
V
EE
GND
RXDGND
PAOFF
INTERLOCK
GND
V
CC
2
5
Test
GND
2
5
NC
CLKSHLD
CLK
SYNLOK
TXD
STDBY
RSSI
SD0
SD1
SD2
SD3
SD4
SD5
SD6
RSSIGND
LOADB
EXTERNAL CONNECTIONS, 40-WAY CONNECTOR
Pin
Name
Description
Frame Ground. Connects to antistatic circuits on DE6003 and internally connected to ground.
1
5V supply pins.
Power Level Control. Sets transmitter power to high (PWRLO = ‘1’) or low (PWRLO = ‘0’).
Diversity Control. This signal is used to select antenna port ANT1 (ANTSEL = ‘0’) or antenna port
ANT2 (ANTSEL = ‘1’). This can be used to make use of diversity to overcome signal nulling due to
destructive interference caused by multipath propagation.
Receive/Transmit control. Switches between Receive (RX/TX = ‘1’) and Transmit (RX/TX = ‘0’)
functions. CMOS compatible with 10k
nominal pull up resistor.
2
5V output from internal switching regulator, powered by external
1
5V supply, V
CC
2
5
, pin 15.
Received Data output.This low drive current data output is the output from the receiver demodulator.
Total load on RXD should be less than 6pF.
2
5V Ground.
Receive Data Ground. See note 1.
Transmitter Power Amplifier Control. PAOFF is used to turn the transmitter power amplifier on and
off, in conjunction with RX/TX.
Connected to ground and can be used to indicate that the DE6003 is connected.See note 2.
1
5V Ground. Internally connected to all other grounds 1, 10, 11,19, 23 and 33.
Positive supply input for internal
2
5V V
EE
generator.
Open circuit for normal mode, high for test mode. For factory use only.
Ground for
2
5V regulator. Internally connected to all ground pins 1,10,11,14,16,18, 20, 23 and 33.
No Connection. These pins are not used, but no connection should be made to them as GPS re-
serves the right to use them for future expansion.
System Clock Ground. See note 1.
System Clock. This synthesiser clock output at 10MHz is also made available during standby as well
as being available during normal operation (it is not a recovered data clock). This output is a constant
current sink/source which must be terminated such as to keep its voltage swing low. See note 2.
Synthesiser Lock Monitor. Should only be used to indicate PLL failure. Lock (SYNLOK = ‘0’) is
defined as all three PLLs in lock. Unlock (SYNLOK = ‘1’) is defined as an Error Condition. Note that
when switching channels unlock may occur for short periods while locking on new channel.
Transmitter Data Input. CMOS compatible with no pull up/pull down resistor.
Standby . When low, disables radio function, placing all ICs into a low current mode; however, the
10MHz clock and the
2
5V regulator continue to run in Standby mode, providing a clock
and
2
5V output on the 40-way connector. CMOS compatible with 30k
nominal pull down resistor.
Receive Signal Strength Indicator. Received in-band signal level monitor. The analog RSSI output
increases monotonically from 0V to
1
3V proportional to the logarithm of the input signal power.
Source impedance is 10k
.
Channel Select Code, SD6:0. These 7 data lines determine the channel used for both transmit and
receive.They are latched on the falling edge of LOADB and implemented on the rising edge of LOADB.
and are CMOS compatible with 30k
nominal pull down resistors. SeeTables 3 and 4.
Received Signal Strength Indicator Ground. Internally connected to all ground pins 1, 10,14,16,18,19,20
and 23.
Channel Select Load Pulse. This active low pulse loads SD (6:0) code into a data latch to set the
required channel. CMOS compatible with 30k
nominal pull up resistor. See Tables 3 and 4.
1
2,4,6
3
5
7
8
9
10
11
12
13
14,16,18,20
15
17
19
21,22,24,
26,27
23
25
28
29
30
31
32
34
35
37
39
36
38
33
40
NOTES. 1. All ground pins (1, 10, 11, 14, 16, 18, 19, 20, 23 and 33) are internally connected. 2. See AN142, Designing with the DE6003, for
further information.
Table 2