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參數(shù)資料
| 型號(hào)： | DEM-ADS83XE |
| 英文描述： | DEM-ADS83xE - EVALUTION FIXTURE |
| 中文描述： | DEM的ADS83xE - EVALUTION夾具 |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大?。?/td> | 206K |
| 代理商： | DEM-ADS83XE |
5
DEM-ACF2101BP
FIGURE 6. Block Diagram of Using the ACF2101BP with a
Voltage Input Instead of a Current Input.
The outputs of the counter will change the state of the flip-
flops depending on the settings of the matrix switches. The
RESET, SELECT, and HOLD control signals are the same
for both sides of the dual ACF2101BP. This is
not
a
requirement for ACF2101 operation. The RESET, SELECT
and HOLD control lines were hard-wired on this board to
make it easier to use.
The rising edge of the trigger initiates the clocking sequence
shown in Figure 8. After a delay the switching signals (row
1 through row 10) that will ultimately control the RESET,
SELECT, and HOLD control pins begin. Each row follows
the preceding row with a rising edge delay of t
. The
pulse width, t
, is changed by adjusting the value of RV1
potentiometer on the board. The nominal range of t
is
6ns to 36
μ
s. The trigger frequency ranges from 2Hz to
20kHz to give a range of cycle times from 500ms to 50
μ
s.
All of the signals from the counter, U1, are connected to the
rows of the switch matrix, SW1. The signals on the rows of
SW1 can be switched into the columns by toggling the
switches on the matrix. RESET is controlled by columns B
and C. The rising edge of C initiates a logic low on the
RESET pin, which closes the RESET switches on both sides
of the dual ACF2101BP (U5). The rising edge of B initiates
a logic high on the RESET pin, which opens the RESET
switches of the ACF2101BP. SELECT is controlled by
columns E and D. The rising edge of E initiates a logic low
on the SELECT pin, which closes the SELECT switches on
both sides of the dual ACF2101BP. The rising edge of D
initiates a logic high on the SELECT pin, which opens the
SELECT switches of the ACF2101BP. HOLD is controlled
by columns G and F. A rising edge of G initiates a logic high
on the HOLD pin, which opens the HOLD switches on both
sides of the dual ACF2101BP. A rising edge of F initiates a
logic low on the HOLD pin, which closes the HOLD
switches of the ACF2101BP. The logic table is shown
below.
Sw Com
Sw Out
C
F
Out
Cap
In
Sw In
Com
R
3
or R
4
+V
IN
L
IN
Select
Reset
Hold
C
3
or
C
4
1/2 ACF2101
100pF
Reset
Hold
V
OUT
Examples of switching arrangements for the DEM-
ACF2101BP are shown in Figure 9.
FACTORY TIMING AND TEST CIRCUIT
The block diagram of the analog portion of the DEM-
ACF2101BP and timing configuration used to test the board
is shown in Figure 10. The setting of column A on SW1
determines the clock cycle of the counter, U1. Column A is
set to Row 0 to give the longest clock cycle and the most
programming flexibility. The REF102 is a 10V reference
chip. Two 10M
resistors are used to generates two 1
μ
A
current sources, which sink into SW IN A and SW IN B of
the ACF2101BP. C
and C
are used during test to prevent
the hold switch input from exceeding 0.5V. The timing
circuit is adjusted to a 20
μ
s pulse width. Operation of the
clock and the ACF2101 is verified.
LAYOUT CONSIDERATIONS
Care was taken in the layout of this board to ensure the best
performance of the ACF2101BP. The inputs of the
ACF2101BP are carefully guarded to prevent excess cur-
rents from being capacitively coupled into the summing
junction of the ACF2101 amplifier. Since this is a four-layer
board, we found that the power planes were critical in this
case and had to be removed from the area.
CLOCK LOGIC
EDGE
ACF2101 SWITCH
AFFECTED
NEW ACF2101
SWITCH CONDITION
SW1
A
B
C
D
E
F
G
H
J
K
No Connect
Rising Edge
Rising Edge
Rising Edge
Rising Edge
Rising Edge
Rising Edge
No Connect
No Connect
No Connect
RESET
RESET
SELECT
SELECT
HOLD
HOLD
OPEN
CLOSED
OPEN
CLOSED
CLOSED
OPEN
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