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| 型號(hào)： | DEMO56F8014-EE |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 26/124頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DEMO FOR 56F8014 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | 56F8014 |
| 所含物品： | 板，線纜，CD，電源 |
| 配用： | APMOTOR56F8000E-ND - KIT DEMO MOTOR CTRL SYSTEM |
| 相關(guān)產(chǎn)品： | MC56F8014VFAE-ND - IC DIGITAL SIGNAL CTRLR 32-LQFP |
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Electrical Design Considerations
56F8014 Technical Data, Rev. 11
Freescale Semiconductor
121
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink. Because of the
experimental difficulties with this technique, many engineers measure the heat sink temperature and then
back-calculate the case temperature using a separate measurement of the thermal resistance of the
interface. From this case temperature, the junction temperature is determined from the junction-to-case
thermal resistance.
12.2 Electrical Design Considerations
Use the following list of considerations to assure correct operation of the 56F8014:
Provide a low-impedance path from the board power supply to each VDD pin on the 56F8014 and from the
board ground to each VSS (GND) pin
The minimum bypass requirement is to place 0.01–0.1
μF capacitors positioned as close as possible to the
package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of
the VDD/VSS pairs, including VDDA/VSSA. Ceramic and tantalum capacitors tend to provide better
tolerances.
Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND)
pins are as short as possible
Bypass the VDD and VSS with approximately 100μF, plus the number of 0.1μF ceramic capacitors
Ψ
JT
=
Thermal characterization parameter (oC/W)
PD
=
Power dissipation in package (W)
CAUTION
This device contains protective circuitry to guard
against damage due to high static voltage or electrical
fields. However, normal precautions are advised to
avoid
application
of
any
voltages
higher
than
maximum-rated voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused inputs are
tied to an appropriate voltage level.
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