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參數(shù)資料
| 型號： | DG2019DN-T1-E4 |
| 廠商： | Vishay Siliconix |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SWITCH DUAL SPDT 16QFN |
| 標準包裝： | 2,500 |
| 功能： | 開關(guān) |
| 電路： | 4 x SPDT - NC/NO |
| 導(dǎo)通狀態(tài)電阻： | 8 歐姆 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 1.8 V ~ 5.5 V |
| 電流 - 電源： | 10nA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 16-QFN（3x3） |
| 包裝： | 帶卷 (TR) |
Vishay Siliconix
DG2018, DG2019
Document Number: 72342
S-82626-Rev. C, 03-Nov-08
www.vishay.com
1
Low Voltage, Dual DPDT and Quad SPDT Analog Switches
FEATURES
Low voltage operation (1.8 V to 5.5 V)
Low on resistance
- RDS(on): 6 Ω at 2.7 V
Low voltage logic compatible
- DG2019: VINH = 1 V
High bandwidth: 180 MHz
QFN-16 package
BENEFITS
Ideal for both analog and digital signal switching
Reduced power consumption
High accuracy
Reduced PCB space
Fast switching
Low leakage
APPLICATIONS
Cellular phones
Audio and video signal routing
PCMCIA cards
Battery operated systems
Portable instrumentation
DESCRIPTION
The DG2018 and DG2019 are low voltage, single supply
analog switches. The DG2018 is a dual double-pole/double-
throw (DPDT) with two control inputs that each controls a
pair of single-pole/double-throw (SPDT). The DG2019 uses
one control pin to operate four independent SPDT switches.
When operated on a + 3 V supply, the DG2018’s control pins
are compatible with 1.8 V digital logic. The DG2019 has an
available feature of a VL pin that allows a 1.0 V threshold for
the control pin when VL is powered with 1.5 V.
Built on Vishay Siliconix’s low voltage submicron CMOS
process, the DG2018 and DG2019 are ideal for high
performance switching of analog signals; providing low on-
resistance (6
Ω at + 2.7 V), fast speed (T
on, Toff at 42 ns and
16 ns), and a bandwidth that exceeds 180 MHz.
The DG2018 and DG2019 were designed to offer solutions
that extend beyond audio/video functions, to providing the
performance required for today’s demanding mixed-signal
switching in portable applications.
An epitaxial layer prevents latch-up. Brake-before-make is
guaranteed for all SPDT’s. All switches conduct equally well
in both directions when on, and blocks up to the power
supply level when off.
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
IN1, IN2
NO4
COM2
NO2
NC3
IN3, IN4
NC1
COM4
1
2
3
12
11
10
49
56
8
16
15
14
13
NC2
GND
NO3 COM3
COM1 NO1
V+
NC4
Top View
DG2018DN
QFN-16 (3 X 3)
7
TRUTH TABLE
IN1, IN2
Logic
NC1 and NC2
NO1 and NO2
0ON
OFF
1OFF
ON
IN3, IN4
Logic
NC3 and NC4
NO3 and NO4
0ON
OFF
1OFF
ON
ORDERING INFORMATION
Temp. Range
Package
Part Number
- 40 °C to 85 °C
QFN-16 (3 x 3 mm)
DG2018DN
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DG201A | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Quad SPST CMOS Analog Switches |
| DG201A WAF | 制造商:Harris Corporation 功能描述: |
| DG201A_01 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Quad SPST, CMOS Analog Switches |
| DG201A_06 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Quad SPST CMOS Analog Switches |
| DG201A_MIL | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:Monolithic Quad SPST CMOS Analog Switches |
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