參數(shù)資料
型號(hào): DG202B
英文描述: Improved Quad CMOS Analog Switches(131.01 k)
中文描述: 改進(jìn)的四CMOS模擬開(kāi)關(guān)(131.01十一)
文件頁(yè)數(shù): 6/11頁(yè)
文件大小: 447K
代理商: DG202B
D
Quad SPST CMOS Analog Switches
6
_______________________________________________________________________________________
R
DS(ON)
AT ANALOG SIGNAL LEVEL
-10V
165
125
POWER SUPPLIES
-5V
350
+5V
380
+10V
250
160
-15V
135
+15V
155
±5V
±10V
±15V
Typical R
DS(ON)
vs. Power Supplies for Maxim
s DG202, and DG212
this current is required to be kept to low (μA) levels
then the addition of external protection diodes is rec-
ommended.
To provide protection for overvoltages up to 20V above
the supplies, a 1N4001 or 1N914 type diode should be
placed in series with the positive and negative supplies
as shown in Figure 2. The addition of these diodes will
reduce the analog signal range to 1V below the posi-
tive supply and 1V above the negative supply.
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
DG202
DG212
IN4001
-15V
IN4001
+15V
Figure 2. Protection against Fault Conditions
V
O
V
O
t
OFF1
t
OFF2
t
OFF
V
S
= +2V
R
L
1k
D
1
S
1
IN
1
C
L
35pF
V-
V
O
50%
3V
0
V
S
0
V+
GND
0.9
0.1
0.9
V
O
LOGIC
INPUT
SWITCH
INPUT
SWITCH
OUTPUT
tr < 20ns
tf < 20ns
LOGIC 1 SW ON
SWITCH
INPUT
V
O
= V
S
LOGIC
INPUT
0V
-15V
+15V
(REPEAT TEST FOR IN
2
, IN
3
, AND IN
4
)
SWITCH
OUTPUT
R
L
R
L
+
r
DS(ON)
TOP VIEW
16
15
14
13
5
1
2
3
4
12
11
10
9
6
7
8
S1
V-
GND
S4
S2
V+
N.C.
S3
D1
IN1
IN2
D2
D4
IN4
IN3
D3
DG202
DG212
QFN
Pin Configurations (continued)
Figure 1. Switching Time
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