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5
FN3284.11
November 20, 2006
FIGURE 2A. MEASUREMENT POINTS
CL includes fixture and stray capacitance.
FIGURE 2B. TEST CIRCUIT
FIGURE 2. BREAK-BEFORE-MAKE TIME
FIGURE 3A. MEASUREMENT POINTS
FIGURE 3B. TEST CIRCUIT
FIGURE 3. CHARGE INJECTION
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. INSERTION LOSS TEST CIRCUIT
Test Circuits and Waveforms (Continued)
90%
3V
0V
tD
0V
LOGIC
INPUT
SWITCH
OUTPUT
SWITCH
OUTPUT
VS1
VS2
90%
tD
0V
(VO1)
(VO2)
LOGIC
INPUT
VS1 = 10V
IN1
V+
D1
RL1
CL1
VO1
GND
V-
VL
0V
-15V
5V
+15V
RL = 300Ω
CL = 35pF
D2
RL2
CL2
VO2
VS2 = 10V
VO
ΔVO
INX
ON
OFF
ON
Q =
ΔVO x CL
SWITCH
OUTPUT
V+
D1
CL
VO
V-
RG
VG
VL
0V
-15V
5V
+15V
GND
ANALYZER
RL
+15V
SIGNAL
GENERATOR
V+
C
V-
-15V
C
0V, 2.4V
VS
VD
INX
GND
+5V
VL
C
ANALYZER
RL
+15V
SIGNAL
GENERATOR
V+
C
V-
-15V
C
0V, 2.4V
VS
VD
INX
GND
+5V
VL
C