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參數(shù)資料
| 型號： | DG419LEUA+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 13/13頁 |
| 文件大小： | 0K |
| 描述： | IC SWITCH SPDT 8UMAX |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 功能： | 開關(guān) |
| 電路： | 1 x SPDT - NC/NO |
| 導(dǎo)通狀態(tài)電阻： | 100 歐姆 |
| 電壓電源： | 單/雙電源 |
| 電壓 - 電源，單路/雙路(±)： | 9 V ~ 36 V，±4.5 V ~ 20 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-uMAX |
| 包裝： | 帶卷 (TR) |
DG417L/DG418L/DG419L
35
, SPST/SPDT, +3V
Logic-Compatible Analog Switches
_______________________________________________________________________________________
9
Applications Information
Power-Supply
Sequencing-Free Operation
Most CMOS switches require specific power-supply
sequencing in order to prevent device latchup. The
older DG417/DG418/DG419 devices require a proper
power-supply sequence of V+, VL, then V-. Otherwise,
it is necessary to add signal diodes to the circuit in
order to prevent potential latchups. The new
DG417L/DG418L/DG419L devices eliminate the need
for a VL input and allow any power-up sequence. Do
not exceed the absolute maximum ratings because
stresses beyond the listed ratings may cause perma-
nent damage to the devices.
+3V
0
VCOM
0.9 x VOUT
LOGIC
INPUT
V-
RL
300
GND
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
NO
COM
NC
V+
CL
35pF
+10V
tD
IN
V+
V-
VOUT
LOGIC
INPUT
DG419L
Figure 4. Charge Injection
VGEN
GND
NC OR
NO
CL
1nF
VOUT
V-
V+
N.C.
VOUT
IN
OFF
ON
OFF
VOUT
Q =
VOUT x CL
COM
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
OFF
ON
OFF
IN
VIN = +3V
DG417L
DG418L
DG419L
V+
Figure 3. DG419L Break-Before-Make Interval
______________________________________Test Circuits/Timing Diagrams (continued)
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