5
FN3586.10
June 4, 2007
Test Circuits and Waveforms
VO is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing
edge of the output waveform.
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
FIGURE 3. CROSSTALK TEST CIRCUIT
FIGURE 4. OFF ISOLATION TEST CIRCUIT
NOTE: Logic input waveform is inverted for switches that have
the opposite logic sense.
50%
tr < 20ns
tf < 20ns
tOFF
80%
3V
0V
VS
0V
tON
VO
LOGIC
INPUT
SWITCH
INPUT
SWITCH
OUTPUT
80%
Repeat test for Channels 2, 3 and 4.
For load conditions, see Specifications. CL includes fixture and
stray capacitance.
V
O
V
S
R
L
R
L
r
DS ON
()
+
------------------------------------
=
SWITCH
INPUT
LOGIC
INPUT
S1
IN1
3V
V+
D1
RL
CL
VO
GND
V-
VL
SWITCH
ΔVO
INX
OFF
ON
INX
OFF
ON
Q =
ΔVO x CL
(DG444)
(DG445)
OUTPUT
V+
D1
CL
VO
GND
V-
VIN = 3V
RG
VG
VL
0V, 2.4V
ANALYZER
+15V
V+
C
VS
10dBm
SIGNAL
GENERATOR
RL
GND
IN1
VD
IN2
50
Ω
0V, 2.4V
NC
V-
-15V
C
VD
ANALYZER
RL
+15V
10dBm
SIGNAL
GENERATOR
V+
C
V-
-15V
C
0V, 2.4V
VS
VD
INX
GND
DG444, DG445