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參數(shù)資料
| 型號(hào)： | DG527 |
| 廠商： | Intersil Corporation |
| 英文描述： | Analog CMOS Latchable Multiplexers |
| 中文描述： | 模擬CMOS鎖存多路復(fù)用器 |
| 文件頁(yè)數(shù)： | 8/16頁(yè) |
| 文件大小： | 308K |
| 代理商： | DG527 |
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12-8
Minimum Input Timing Requirements
Over Full Temperature Range
PARAMETER
MEASURED TERMINAL
MIN
UNITS
WRITE Pulse Width, t
WW
WR, See Figure 1
300
ns
A, EN Data Valid After WRITE (Stabilization Time), t
DW
A
0
, A
1
, (A
2
), EN, WR; See Figure 1
180
ns
A, EN Data Valid After WRITE (Hold Time), t
WD
A
0
, A
1
, (A
2
), EN, WR; See Figure 1
30
ns
RESET Pulse Width, t
RS
RS, (Note 6), V
S
= 5V, See Figure 2
500
ns
NOTES:
1. Signals on V
S
, V
D
or V
IN
exceeding V+ or V- will be clamped by internal diodes. Limit diode forward current to maximum current ratings.
2. Typical values are for design aid only, not guaranteed and not subject to production testing.
3. The algebraic convention whereby the most negative value is a minimum, and most positive value is a maximum, is used in this datasheet.
VD
4.
, where V
S
= input to OFF switch, and V
D
= output due to V
S
.
5. I
D(ON)
is leakage from driver into “ON” switch.
6. Period of Reset (RS) pulse must be at least 50
μ
s during or after power ON.
7. Parameter not tested. Parameter guaranteed by design or characterization.
Test Circuits and Waveforms
FIGURE 1. WR TIMING WAVEFORMS
FIGURE 2. RS TIMING WAVEFORMS
FIGURE 3A. t
TRANSITION
SWITCHING TIME TEST CIRCUIT
Similar connections for DG526
FIGURE 3B. t
TRANSITION
SWITCHING TIME TEST CIRCUIT
Similar connections for DG527
OFF Isolation
20
---------
=
3V
0
WR
A
0
, A
1
, (A
2
)
3V
0
1.5V
t
WW
t
DW
t
WD
2.0V
0.8V
EN
3V
0
RS
V
O
0V
SWITCH
OUTPUT
1.5V
t
RS
t
OFF(RS)
0.8V
O
EN
RS
A
0
S
2
THRU S
7
A
1
A
2
LOGIC
INPUT
50
+2.4V
SWITCH
OUTPUT
35pF
1M
+15V
-15V
+10V
±
10V
GND
WR
V-
DG528
S
1
S
8
D
V+
V
D
EN
RS
S
2A
THRU S
4A,
A
0
A
1
LOGIC
INPUT
50
+2.4V
SWITCH
OUTPUT
35pF
1M
+15V
-15V
+10V
±
10V
GND
WR
V-
DG529
S
1B
S
4B
D
B
V+
D
A
S
2B
, AND S
3B
V
DB
DG526, DG527, DG528, DG529
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