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| 型號(hào)： | DJIXEEAD0SE000 |
| 廠商： | Intel Corp. |
| 英文描述： | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| 中文描述： | 先進(jìn)的8端口10/100 Mbps的物理層收發(fā)器 |
| 文件頁(yè)數(shù)： | 85/226頁(yè) |
| 文件大?。?/td> | 1575K |
| 代理商： | DJIXEEAD0SE000 |
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
87
Table 28. Intel
LXT9785/LXT9785E MDIO Control Interface Signals – BGA23
Ball/Pin
Designation
Symbol
Type
1
Signal Description
2,3,
4
BGA23
PQFP
F3,
A10
64
25
MDIO0
MDIO1
I/O, TS, SL,
IP
Management Data Input/Output.
Bidirectional serial data channel for communication
between the PHY and MAC or switch ASIC. Only
MDIO0 is used when 1x8 port sectionalization is
selected. In 2x4 port sectionalization mode, MDIO0
accesses ports 0-3 and MDIO1 accesses ports 4-7.
Refer to
Figure 21 “Intel LXT9785/LXT9785E Typical
SS-SMII Quad Sectionalization Diagram” on page 140
.
F1,
C9
67
26
MDINT0
MDINT1
OD, TS, SL,
IP
Management Data Interrupt.
When Register bit 18.1 = 1, an active Low output on this
Pin indicates status change. Only MDINT0 is used when
1x8 port sectionalization is selected. In 2x4 port
sectionalization mode, MDINT0 is associated with ports
0-3 and MDINT1 is associated with ports 4-7. Refer to
Figure 21 “Intel LXT9785/LXT9785E Typical SS-SMII
Quad Sectionalization Diagram” on page 140
.
E1,
B10
63
24
MDC0
MDC1
I, ST, ID
Management Data Clock.
Clock for the MDIO serial data channel. Maximum
frequency is 20 MHz. Only MDC0 is used when 1x8 port
sectionalization is selected. In 2x4 port
sectionalization mode, MDC0 clocks ports 0-3 register
accesses and MDC1 clocks ports 4-7 register accesses.
Refer to
Figure 21 “Intel LXT9785/LXT9785E Typical
SS-SMII Quad Sectionalization Diagram” on page 140
.
L1
84
MDDIS
I, ST, ID
Management Disable.
When MDDIS is tied High, the MDIO port is completely
disabled and the Hardware Control Interface pins set
their respective bits at power up and reset.
When MDDIS is pulled Low at power up or reset, via the
internal pull-down resistor or by tieing it to ground, the
Hardware Control Interface Pins control only the initial
or “default” values of their respective register bits. After
the power-up/reset cycle is complete, bit control reverts
to the MDIO serial channel.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-
Down.
2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID
resistors are also disabled when the output is enabled.
3. MDIO[0:1] and MDINT[0:1] outputs are three-stated in H/W Power-Down mode and during H/W reset.
4. Supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,
where X is the register number (0-32) and Y is the bit number (0-15).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DJIXEEAD0SE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEECD0QE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEECD0QE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEECD0SE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEECD0SE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DJIXEEAD0SE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEECD0QE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEECD0QE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEECD0SE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEECD0SE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
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