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| 型號(hào)： | DJIXEECD0SE000 |
| 廠商： | Intel Corp. |
| 英文描述： | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| 中文描述： | 先進(jìn)的8端口10/100 Mbps的物理層收發(fā)器 |
| 文件頁(yè)數(shù)： | 120/226頁(yè) |
| 文件大小： | 1575K |
| 代理商： | DJIXEECD0SE000 |
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
122
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
physical connection, a specific protocol that runs across the connection, and an internal set of
addressable registers. Some registers are required and their functions are defined by the IEEE
802.3 specification. Additional registers allow for expanded functionality. Specific bits in the
registers are referenced using an “X.Y” notation, where X is the register number (0-32) and Y is
the bit number (0-15).
The physical interface consists of a data line (MDIO) and clock line (MDC). Operation of this
interface is controlled by the MDDIS input pin. When MDDIS is High, all the MDIOs are
completely disabled. The Hardware Control Interface provides primary configuration control.
When MDDIS is Low, the MDIO port is enabled for both read and write operations and the
Hardware Control Interface is not used.
Note:
The BGA15 package does not support the MDDIS pin.
The timing for the MDIO Interface is shown in
Table 79, “Intel LXT9785/LXT9785E MDIO
Timing Parameters” on page 197
. MDIO read and write cycles are shown in
Figure 9, “Intel
LXT9785/LXT9785E Management Interface Read Frame Structure” on page 122
and Figure 10,
“Intel LXT9785/LXT9785E Management Interface Write Frame Structure” on page 122
.
The protocol allows one controller to communicate with multiple LXT9785/LXT9785E chips. Pins
ADD_<4:0> determine the base address. Each port adds its port number to the base address to
obtain its port address as shown in
Figure 11
.
The BGA15 package uses a similar scheme where the ADD_[2:0] bits internally set to 0 and the
ADD_[4:3] bits are used to select from four base addresses (0x00000b, 0x01000b, 0x10000b, or
0x11000b.
Figure 9. Intel
LXT9785/LXT9785E Management Interface Read Frame Structure
Figure 10. Intel
LXT9785/LXT9785E Management Interface Write Frame Structure
MDC
MDIO
(Read)
High Z
32 "1"s
0
1
1
0
Preamble
ST
Op Code
PHY Address
Turn
Around
Z
0
A4
A3
A0
R4
R3
R0
Register Address
D15
D14
D1
Data
Write
Read
D15
D14
D1
D0
Idle
MDC
MDIO
(Write)
32 "1"s
0
1
0
1
Preamble
ST
Op Code
PHY Address
Turn
Around
1
0
A4
A3
A0
R4
R3
R0
Register Address
D15
D14
D1
D0
Data
Idle
Idle
Write
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DJIXEECD0SE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEEED0QE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEEED0QE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEEED0SE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEEED0SE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DJIXEECD0SE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEEED0QE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEEED0QE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEEED0SE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEEED0SE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
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