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參數(shù)資料
| 型號(hào)： | DJIXELAD0QE000 |
| 廠商： | Intel Corp. |
| 英文描述： | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| 中文描述： | 先進(jìn)的8端口10/100 Mbps的物理層收發(fā)器 |
| 文件頁(yè)數(shù)： | 165/226頁(yè) |
| 文件大?。?/td> | 1575K |
| 代理商： | DJIXELAD0QE000 |
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
167
The transmit pair should contain a balance offset in the pull-up resistors to prevent PHY-to-
fiber transceiver crosstalk amplification in power-down, loopback, and reset states (see fiber
interface application note)
The receive pair should be DC-coupled with an emitter current path for the fiber transceiver
The signal detect pin should be DC-coupled with an emitter current path for the fiber
transceiver
Refer to the fiber transceiver manufacturer’s recommendations for termination circuitry.
Figure 36
shows a typical example of an LXT9785/LXT9785E-to-3.3 V fiber transceiver interface.
The following occurs in 5 V fiber transceiver applications as shown in
Figure 37
:
The transmit pair should be AC-coupled and re-biased to 5 V PECL input levels
The transmit pair should contain a balance offset in the pull-up resistors to prevent PHY-to-
fiber transceiver crosstalk amplification in power-down, loopback, and reset states (see fiber
interface application note)
The receive pair should be AC-coupled with an emitter current path for the fiber transceiver
and re-biased to 1.2 V
The signal detect pin on a 5 V fiber transceiver interface should use the logic translator
circuitry as shown in
Figure 38
.
Refer to the fiber transceiver manufacturer’s recommendations for termination circuitry.
Figure 37
shows a typical example of an LXT9785/LXT9785E-to-5 V fiber transceiver interface, while
Figure 38
shows the interface circuitry for the logic translator.
5.2.6
LED Circuit
Each Direct Drive LED has a corresponding open-drain pin. The LEDs are connected through a
current-limiting resistor to a positive-voltage rail. The LEDs are turned on when the output pin
drives Low. The open-drain LED pins are 5 V tolerant, allowing use of either a 3.3 V or 5 V rail (a
2.5 V rail is unlikely to work with standard forward voltage LEDs). A 5 V rail eases LED
component selection by allowing more common, high-forward voltage LEDs to be used. Refer to
Figure 33
for a circuit illustration.
Figure 33. LED Circuit
R
V
LED
Inside
IC
Outside
IC
LED
n
_m
VCCIO < V
LED
< 5 V + 5%
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DJIXELAD0QE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXELAD0SE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXELAD0SE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXELCD0QE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXELCD0SE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DJIXELAD0QE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXELAD0SE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXELAD0SE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXELCD0QE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXELCD0QE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
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