LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
134
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Figure 16. Intel
LXT9785/LXT9785E Typical SMII Quad Sectionalization Diagram
M
SYNC0
L
1
A
(
SYNC1
4
M
M
8
SYNC0
8
125 MHz Sourced
Externally or from
Switch ASIC
4
L
1
A
(
SYNC0
4
4
MDC0
MDC0
MDINT0
MDIO0
MDIO0
MDIO0
MDC0
8
8
4
4
MDIO1
MDC1
RefClk0
RefClk1
TxData
n
RefClk0
TxData
n
RefClk1
RefClk0 RefClk1
RxData
n
TxData
n
RxData
n
RxData
n
MDINT1
MDINT0
MDINT0
TxData
n
RxData
n
SECTION
SECTION
SECTION
VCC
L
Typical SMII Interface in a
24-Port System