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| 型號(hào)： | DJIXELED0SE001 |
| 廠商： | Intel Corp. |
| 英文描述： | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| 中文描述： | 先進(jìn)的8端口10/100 Mbps的物理層收發(fā)器 |
| 文件頁(yè)數(shù)： | 164/226頁(yè) |
| 文件大小： | 1575K |
| 代理商： | DJIXELED0SE001 |
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
166
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Place the magnetics as close as possible to the LXT9785/LXT9785E.
Keep transmit pair traces as short as possible; both traces should have the same length.
Avoid vias and layer changes as much as possible.
Keep the transmit and receive pairs apart to avoid cross-talk.
Route the transmit pair adjacent to a ground plane. The optimum arrangement is to place the
transmit traces two to three layers from the ground plane, with no intervening signals.
Improve EMI performance by filtering the TPO center tap. A single ferrite bead rated at 400
mA may be used to supply center tap current to all ports.
5.2.4.1
Magnetic Requirements
The LXT9785/LXT9785E requires a 1:1 ratio for both the receive transformers and the transmit
transformers. The transmit isolation voltage should be rated at 1.5 kV to protect the circuitry from
static voltages across the connectors and cables. The LXT9785/LXT9785E is a current driven
transceiver that requires an external voltage (center tap) to drive the transmit signal. In order to
support the Auto-MDIX functionality of the LXT9785/LXT9785E, the magnetic must provide a
center tap for both the transmit and receive magnetic winding, with both connected to VCCT. See
the LXT9785/LXT9785E Design and Layout Guide (249509-001) for magnetic testing with the
LXT9785/LXT9785E. Before committing to a specific component, designers should contact the
manufacturer for current product specifications, and validate the magnetics for the specific
application.
Table 50
provides the magnetics requirements.
5.2.5
The Fiber Interface
The fiber interface consists of an LVPECL transmit and receive pair to an external fiber-optic
transceiver. Both 3.3 V fiber-optic transceivers and 5 V fiber-optic transceivers can be used with
the LXT9785/LXT9785E. See the 100BASE-FX Fiber Optic Transceivers-Connecting a PECL/
LVPECL Interface Application Note (document number 250781) for detailed information on fiber
interface designs and recommendations for Intel PHYs.
The following should occur in 3.3 V fiber transceiver applications as shown in
Figure 36
:
The transmit pair should be AC-coupled with 2.5 V supplies and re-biased to 3.3 V LVPECL
levels
Table 50. Intel
LXT9785/LXT9785E Magnetics Requirements
Parameter
Min
Nom
Max
Units
Test Condition
Rx turns ratio
–
1:1
–
–
Tx turns ratio
–
1:1
–
–
Insertion loss
0.0
0.6
1.1
dB
Primary inductance
350
–
–
μ
H
Transformer isolation
–
2
–
kV
Differential to common mode
rejection
40
–
–
dB
.1 to 60 MHz
35
–
–
dB
60 to 100 MHz
Return Loss
-16
–
–
dB
30 MHz
-10
–
–
dB
80 MHz
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| DJIXFLCD0SE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DJIXEPAD0QE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEPAD0QE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEPAD0SE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEPAD0SE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEPCD0QE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
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