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| 型號(hào)： | DJIXEPCD0QE000 |
| 廠商： | Intel Corp. |
| 英文描述： | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| 中文描述： | 先進(jìn)的8端口10/100 Mbps的物理層收發(fā)器 |
| 文件頁(yè)數(shù)： | 122/226頁(yè) |
| 文件大小： | 1575K |
| 代理商： | DJIXEPCD0QE000 |
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
124
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Auto-negotiation complete.
Speed status change.
Duplex status change.
Link status change.
Isolate status change.
4.3.10
Global Hardware Control Interface
The LXT9785/LXT9785E provides a Hardware Control Interface for applications where the
MDIO is not desired. Refer to
“Initialization” on page 126
for additional details.
4.3.11
FIFO Initial Fill Values
The FIFO initial fill value sets the number of bits required to be written into the FIFO before the
process of reading the packet out of the FIFO is started. The read operation is aligned on nibble
boundaries because the FIFO is one nibble wide. The read clock on the RMII and SMII interfaces
may occur any time within the next available nibble. Therefore, the effective size of the FIFO is
one nibble less than the selected size.
Large initial fill FIFO settings alter both the data-path latency and the InterFrame Gap (IFG) output
on the RMII and SMII interfaces. The latency values are increased or decreased depending on the
number of bits the FIFO size is increased or decreased. The IFG may decrease up to twice the size
of the initial fill FIFO setting. When the following three conditions are met, the IPG on the RMII
and SMII interfaces may become nonexistent between packets, effectively concatenating the
packets into one long corrupted packet:
The frequency difference between the link partner and the local LXT9895 device exceed
200 ppm (the IEEE standard requirement).
Jumbo packets (8192 byte packets or longer) are used.
Packets on the wire occur with minimum Inter-Packet Gap (IPG) of 96 bit times.
The concatenation of the packets is flagged by the MAC as a CRC error and possibly an oversized
packet depending upon the length indication capabilities of the MAC. The possibility of packet
concatenation can be minimized on the RMII interface by setting the initial fill FIFO Register bits
18.15:14 to 01. The FIFO setting bits should be set to 10 for the SMII interfaces.
Figure 12. Intel
LXT9785/LXT9785E Interrupt Logic
Force Interrupt
Interrupt Enable
Event X Enable Reg
Interrupt Pin
AND
OR
AND
.
Per port
Per Event
Port
Combine
Logic
Interrupt (Event) Status Register is cleared on read.
X = Any Interrupt capability
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DJIXEPCD0QE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEPCD0SE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEPCD0SE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEPED0QE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEPED0QE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DJIXEPCD0QE001 | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEPCD0SE000 | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEPCD0SE001 | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEPED0QE000 | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEPED0QE001 | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
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