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參數(shù)資料
| 型號： | DJIXEPED0QE000 |
| 廠商： | Intel Corp. |
| 英文描述： | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| 中文描述： | 先進(jìn)的8端口10/100 Mbps的物理層收發(fā)器 |
| 文件頁數(shù)： | 151/226頁 |
| 文件大?。?/td> | 1575K |
| 代理商： | DJIXEPED0QE000 |
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
153
4.11.2
Interaction between Processor, MAC, and PHY
The state machines that control the mechanics of the Discovery process reside within the
LXT9785E device. However, control of the power supply and overall system control reside in the
system processor. The processor communicates with the power supply unit (PSU) and switches it
on and off dependant on the data that is supplied by the PHY. The PHY register data is read by the
MAC using the MDIO interface. The required control bits are contained in the PHY device register
map and are discussed in detail in the section labeled
“Management Interface and Control” on
page 153
.
Note:
The details of the processor/MAC interface and the processor/PSU interface are implementation
specific and therefore are out of the scope of this specification.
The following is an overview of the system control for a successful Remote-Power DTE discovery:
1. The discovery process is enabled by the DTE Discovery Process Enable (Dis_EN) Register bit
27.6 and the Auto-Negotiation Enable Register bit 0.12. Writing Register bit 27.6 immediately
affects the Auto-Negotiation Base Page. If already enabled, auto-negotiation should be
restarted after this bit is written to ensure proper operation. Register bit 4.15 is used for manual
control of auto-negotiation next pages and should be left in the default state (cleared).
2. The LXT9785E PHY then tests to see if a Remote-Power DTE is present as the link partner. If
a Remote-Power DTE is found, the Power Enable (Power_EN) Register bit 27.4 is set. The
processor polls this signal via the MAC.
3. Upon detecting a Remote-Power DTE, the processor instructs the power supply to switch on.
Once power has been applied to the DTE, normal negotiation takes place. The processor must
enable the required negotiation process by restarting auto-negotiation, or by setting forced
speed mode after power has been applied. The processor must poll the link-up Register bit 1.2
for the corresponding LXT9785E port, or the link status change interrupt, to ensure that the
link has been established.
4. A time-out must be connected with this feature so that if link is not established within a pre-
determined time period (system dependant), the processor instructs the power supply to switch
off. If link is not established prior to the expiration of the “l(fā)ink fail inhibit timer”, the
LXT9785E restarts negotiation with DTE detection if auto-negotiation mode was used to
establish link with the phone, and the DTE process is still enabled. The LXT9785E restarts
negotiation without DTE detection if either forced speed mode is used to establish link with
the phone, or the DTE process is disabled.
5. If power is applied and link is established, the system must still poll the Link Status Register
bit 1.2 for the corresponding LXT9785E port or the link status change interrupt. This is
required since link status is the only way to know when the Remote-Power DTE is removed or
unplugged. On seeing the Link_Down condition, the processor instructs the power supply to
switch off, and the DTE Discovery begins again or is disabled.
4.11.3
Management Interface and Control
The management and control of the DTE discovery process is via the MDIO port. Each port on the
LXT9785E is capable of running the discovery process, thus each port is independently controlled.
This is achieved by each port having a dedicated set of control and status bits. These bits are found
in Register 27 as follows:
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DJIXEPED0QE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEPED0SE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEPED0SE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFEAD0QE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFEAD0QE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DJIXEPED0QE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEPED0SE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEPED0SE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXF972MBAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXF972MBCA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
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