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參數(shù)資料
| 型號(hào)： | DJIXEPED0SE001 |
| 廠商： | Intel Corp. |
| 英文描述： | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| 中文描述： | 先進(jìn)的8端口10/100 Mbps的物理層收發(fā)器 |
| 文件頁(yè)數(shù)： | 198/226頁(yè) |
| 文件大?。?/td> | 1575K |
| 代理商： | DJIXEPED0SE001 |
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
200
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
27
“Trim Enable Register (Address 27, Hex 1B)”
Refer to
Table 99 on page 216
28
Reserved
N/A
29
“Cable Diagnostics Register (Address 29, Hex 1D)”
Refer to
Table 100 on page 217
30 - 31
Reserved
N/A
Table 83. Control Register (Address 0) (Sheet 1 of 2)
Bit
Name
Description
Type
1
Default
15
RESET
0 = Normal operation
1 = PHY reset
R/W
SC
0
2
14
Loopback
0 = Disable loopback mode
1 = Enable loopback mode
Not recommended to enable auto-negotiation
while in internal loopback operation.
R/W
0
13
Speed Selection
0.6
1
1
0
0
0.13
1 = Reserved
0 = 1000 Mbps (not allowed)
1 = 100 Mbps
0 = 10 Mbps
R/W
LSHR
3,4
12
Auto-Negotiation
Enable
0 = Disable auto-negotiation process
1 = Enable auto-negotiation process
R/W
LSHR
3,4
11
Power-Down
0 = Normal operation
1 = Power-down
R/W
LSHR
3,5
10
Isolate
0 = Normal operation
1 = Electrically isolate PHY from RMII/SMII/SS-
SMII interfaces
R/W
0
9
Restart
Auto-Negotiation
0 = Normal operation
1 = Restart auto-negotiation process
R/W
SC
0
8
Duplex Mode
0 = Half-duplex
1 = Full-duplex
R/W
LSHR
3,4
1. R/W = Read/Write, SC = Self Clearing when operation complete.
2. During a hardware reset, all LHR information is latched in from the pins. During a software reset (0.15), the
LSHR information is not re-read from the pins. This information reverts back to the information that was
read in during the hardware reset. During a hardware rest, register information is unavailable from 1 ms
after de-assertion of the reset. During a software reset (0.15) the registers are available for reading. The
reset bit should be polled to see when the part has completed reset.
3. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as
the pin(s) are latched at startup or hardware reset.
4. Default value of Register bits 0.12, 0.13, and 0.8 are determined by the CFG pins as described in
Table 42,
“Intel LXT9785/9785E Global Hardware Configuration Settings” on page 129
.
5. Default value of Register bit 0.11 is determined by the LINKHOLD configuration pin.
Table 82. Intel
LXT9785/LXT9785E Register Set (Sheet 2 of 2)
Address
Register Name
Bit Assignments
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DJIXFEAD0QE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFEAD0QE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFEAD0SE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFEAD0SE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFECD0QE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DJIXF972MBAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXF972MBCA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXF972MBEA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXF972MCAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXF972MCCA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
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