參數(shù)資料
    型號(hào): DJIXF972MCCA4
    廠商: Intel Corp.
    英文描述: Single-Port 10/100 Mbps PHY Transceiver
    中文描述: 單端口10/100 Mbps的物理層收發(fā)器
    文件頁數(shù): 73/92頁
    文件大小: 666K
    代理商: DJIXF972MCCA4
    Intel
    LXT972M Single-Port 10/100 Mbps PHY Transceiver
    Datasheet
    Document Number: 302875-005
    Revision Date: 27-Oct-2005
    73
    Figure 32. Intel
    LXT972M Transceiver Power-Up Timing
    Table 38. Intel
    LXT972M Transceiver Power-Up Timing
    Parameter
    Symbol
    Min
    Typ
    1
    Max
    Units
    Test Conditions
    Voltage threshold
    v1
    2.9
    V
    Power Up delay
    2
    t1
    300
    μ
    s
    1. Typical values are at 25° C and are for design aid only, not guaranteed, and not subject to production
    testing.
    2. Power-up delay is specified as a maximum value because it refers to the PHY guaranteed performance.
    The PHY comes out of reset after a delay of no more than 300
    μ
    s. System designers should consider this
    value as a minimum value. After threshold v1 is reached, the MAC should delay no less than 300
    μ
    s before
    accessing the MDIO port.
    t1
    VCC
    MDIO, and
    so on
    v1
    B3494-01
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