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參數(shù)資料
| 型號(hào)： | DJIXF972MKCA4 |
| 廠商： | Intel Corp. |
| 英文描述： | Single-Port 10/100 Mbps PHY Transceiver |
| 中文描述： | 單端口10/100 Mbps的物理層收發(fā)器 |
| 文件頁(yè)數(shù)： | 74/92頁(yè) |
| 文件大?。?/td> | 666K |
| 代理商： | DJIXF972MKCA4 |
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Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
74
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
Figure 33. Intel
LXT972M Transceiver RESET_L Pulse Width and Recovery Timing
Table 39. Intel
LXT972M Transceiver RESET_L Pulse Width and Recovery Timing
Parameter
Symbol
Min
Typ
1
Max
Units
Test Conditions
RESET_L pulse width
t1
10
–
–
ns
–
RESET_L recovery delay
2
t2
–
300
μ
s
–
1. Typical values are at 25° C and are for design aid only, not guaranteed, and not subject to production
testing.
2. Reset Recovery Delay is specified as a maximum value because it refers to the PHY guaranteed
performance. The PHY comes out of reset after a delay of no more than 300
μ
s. System designers should
consider this value as a minimum value. After de-asserting RESET_L, the MAC should delay no less than
300
μ
s before accessing the MDIO port.
t2
RESET_L
MDIO, and
so on
t1
B3495-01
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DJIXF972MKEA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXF972MLAA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXP972MLAA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXP972MLCA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXP972MLEA4 | Single-Port 10/100 Mbps PHY Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DJIXF972MKEA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXF972MLAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXF972MLCA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXF972MLEA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXF972MNAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
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