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參數(shù)資料
| 型號(hào)： | DJIXFLAD0QE001 |
| 廠商： | Intel Corp. |
| 英文描述： | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| 中文描述： | 先進(jìn)的8端口10/100 Mbps的物理層收發(fā)器 |
| 文件頁(yè)數(shù)： | 162/226頁(yè) |
| 文件大?。?/td> | 1575K |
| 代理商： | DJIXFLAD0QE001 |
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
164
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
5.0
Application Information
5.1
Design Recommendations
The LXT9785/LXT9785E is designed to comply with IEEE 802.3 requirements to provide
outstanding receive Bit Error Rate (BER), and long-line-length performance. To achieve maximum
performance from the LXT9785/LXT9785E, attention to detail and good design practices are
required.
Refer to the LXT9785 Design and Layout Guide application note for detailed design and
layout information
.
5.2
General Design Guidelines
Adherence to generally accepted design practices is essential to minimize noise levels on power
and ground planes. Up to 50 mV maximum of noise is considered acceptable. High-frequency
switching noise can be reduced, and its effects eliminated, by following these simple guidelines
throughout the design:
Fill in unused areas of the signal planes with solid copper and attach them with vias to a VCC
or ground plane that is not located adjacent to the signal layer.
Use ample bulk and decoupling capacitors throughout the design (a value of 0.01
μ
F is
recommended for decoupling caps).
Provide ample power and ground planes.
Provide termination on all high-speed switching signals and clock lines.
Provide impedance matching on long traces to prevent reflections.
Route high-speed signals next to a continuous, unbroken ground plane.
Filter and shield DC-DC converters, oscillators, etc.
Do not route any digital signals between the LXT9785/LXT9785E and the RJ-45 connectors at
the edge of the board.
Do not extend any circuit power and ground plane past the center of the magnetics or to the
edge of the board. Use this area for chassis ground, or leave it void.
5.2.1
Power Supply Filtering
Power supply ripple and digital switching noise on the VCC plane may cause EMI problems and
degrade line performance. The best approach to this problem is to minimize ground noise as much
as possible using good general techniques and by filtering the VCC plane. It is generally difficult to
predict in advance the performance of any design, although certain factors greatly increase the risk
of having problems:
Poorly-regulated or over-burdened power supplies.
Wide data busses (32-bits+) running at a high clock rate.
DC-to-DC converters.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DJIXFLAD0SE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFLAD0SE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXPEED0QE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXPEED0QE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXPEED0SE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DJIXFLAD0SE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFLAD0SE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFLCD0QE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFLCD0QE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFLCD0SE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
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