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參數(shù)資料
| 型號(hào)： | DJIXP972MLEA4 |
| 廠商： | Intel Corp. |
| 英文描述： | Single-Port 10/100 Mbps PHY Transceiver |
| 中文描述： | 單端口10/100 Mbps的物理層收發(fā)器 |
| 文件頁數(shù)： | 28/92頁 |
| 文件大?。?/td> | 666K |
| 代理商： | DJIXP972MLEA4 |
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Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
28
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
5.3
Operating Requirements
5.3.1
Power Requirements
The LXT972M Transceiver requires three power supply inputs:
VCCA
VCCD
VCCIO
The digital and analog circuits require 3.3 V supplies (VCCA and VCCD). These inputs may be
supplied from a single source. Each supply input must be de-coupled to ground.
An additional supply may be used for the MII (VCCIO). The supply may be either +2.5 V or
+3.3 V. Also, the inputs on the MII interface are tolerant to 5 V signals from the controller on the
other side of the MII interface. For MII I/O characteristics, see
Table 24, “Digital I/O
Characteristics1 - MII Pins” on page 62
.
Note:
Bring up power supplies as close to the same time as possible.
Note:
As a matter of good practice, keep power supplies as clean as possible.
5.3.2
Clock Requirements
5.3.2.1
External Crystal/Oscillator
The LXT972M Transceiver requires a reference clock input that is used to generate transmit
signals and recover receive signals. It may be provided by either of two methods: by connecting a
crystal across the oscillator pins (XI and XO) with load capacitors, or by connecting an external
clock source to pin XI.
The connection of a clock source to the XI pin requires the XO pin to be left open. To minimize
transmit jitter, Intel recommends a crystal-based clock instead of a derived clock (that is, a PLL-
based clock).
A crystal is typically used in NIC applications. An external 25 MHz clock source, rather than a
crystal, is frequently used in switch applications. For clock timing requirements, see
Table 25, “I/O
Characteristics - REFCLK/XI and XO Pins” on page 63
.
5.3.2.2
MDIO Clock
The MII management channel (MDIO) also requires an external clock. The managed data clock
(MDC) speed is a maximum of 8 MHz. For details, see
Table 37, “Intel LXT972M Transceiver
MDIO Timing” on page 72
.
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| DJIXP972MNEA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXP972MPAA4 | Single-Port 10/100 Mbps PHY Transceiver |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| DJIXP972MNAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXP972MNCA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXP972MNEA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXP972MPAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXP972MPCA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
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