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| 型號(hào)： | DJIXPEAD0SE000 |
| 廠商： | Intel Corp. |
| 英文描述： | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| 中文描述： | 先進(jìn)的8端口10/100 Mbps的物理層收發(fā)器 |
| 文件頁(yè)數(shù)： | 156/226頁(yè) |
| 文件大小： | 1575K |
| 代理商： | DJIXPEAD0SE000 |
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
158
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
When a long event (such as duplex status) occurs, it is edge detected and starts the stretch timer.
When the stretch timer expires, the edge detector is reset so that a long event causes another pulse
to be generated from the edge detector. The edge detector resets the stretch timer, causing the LED
driver to remain asserted.
Figure 31 on page 158
shows how the stretch operation functions.
4.12.3
Out-of-Band Signaling
The LXT9785/LXT9785E provides an out-of-band signaling option to transfer status information
across the RMII receive interface. This feature is enabled when Register bit 25.0 = 1 and uses the
RxData(1:0) data bus during the Inter-Packet Gap (IPG) time as shown in
Figure 32
. Out-of-Band
signaling is disabled when Isolate mode is enabled by setting Register 0.10.
Note:
The BGA15 package does not support Out-of-Band Signaling nor the RMII interface.
The two status bits transferred across the RxData bus are software selectable via Register 25 (see
Table 98, “RMII Out-of-Band Signaling Register (Address 25, Hex 19)” on page 215
).
In normal operation, the LXT9785/LXT9785E stuffs the RxData bus with zeros during the IPG. A
software-selectable bit enables the RMII out-of-band signaling feature. Once this bit is set, the
LXT9785/LXT9785E replaces the zeros with selected status bits during the IPG.
Figure 31. Intel
LXT9785/LXT9785E LED Pulse Stretching
Event
LED
Note: The direct drive LED outputs in this diagram are shown as active Low.
stretch
stretch
stretch
Figure 32. Intel
LXT9785/LXT9785E RMII Programmable Out-of-Band Signaling
REFCLK
CRS_DV
RXD(1)
RXD(0)
data
data
data
data
data
data
data
data
status 0
status 0
status 0
status 0
status 0
status 0
status 1
status 1
status 1
status 1
status 1
status 1
0s
status 1
status 0
0s
1. When network activity is detected, the LXT9785/LXT9785E asserts CRS_DV asynchronously with respect
to REFCLK.
2. After CRS_DV is asserted, the LXT9785/LXT9785E zero-stuffs the RxData bits until the received data has
been processed through the FIFO.
3. When network activity ceases, the LXT9785/LXT9785E de-asserts CRS_DV synchronously with respect
to REFCLK. CRS_DV toggles until all data in the FIFO has been processed through the RMII. Once the
FIFO is empty, LXT9785/LXT9785E drives the status bits selected by the Out-of-Band Signaling Register
(refer to
Table 98, “RMII Out-of-Band Signaling Register (Address 25, Hex 19)” on page 215
) on the
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DJIXPEAD0SE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXPECD0QE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXPECD0QE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXPECD0SE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXPECD0SE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DJIXPEAD0SE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXPECD0QE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXPECD0QE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXPECD0SE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXPECD0SE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
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