- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄376723 > DJIXPEED0SE001 (Intel Corp.) Advanced 8-Port 10/100 Mbps PHY Transceivers PDF資料下載
參數(shù)資料
| 型號(hào)： | DJIXPEED0SE001 |
| 廠商： | Intel Corp. |
| 英文描述： | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| 中文描述： | 先進(jìn)的8端口10/100 Mbps的物理層收發(fā)器 |
| 文件頁(yè)數(shù)： | 4/226頁(yè) |
| 文件大?。?/td> | 1575K |
| 代理商： | DJIXPEED0SE001 |
第1頁(yè)第2頁(yè)第3頁(yè)當(dāng)前第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)
Contents
4
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
4.3.7
4.3.8
4.3.9
4.3.10 Global Hardware Control Interface......................................................................124
4.3.11 FIFO Initial Fill Values..........................................................................................124
Operating Requirements...................................................................................................125
4.4.1
Power Requirements...........................................................................................125
4.4.2
Clock/SYNC Requirements .................................................................................125
4.4.2.1
Reference Clock ..................................................................................125
4.4.2.2
TxCLK Signal (SS-SMII only)...............................................................125
4.4.2.3
TxSYNC Signal (SMII/SS-SMII)...........................................................125
4.4.2.4
RxSYNC Signal (SS-SMII only)...........................................................125
4.4.2.5
RxCLK Signal (SS-SMII only)..............................................................126
Initialization.......................................................................................................................126
4.5.1
MDIO Control Mode.............................................................................................126
4.5.2
Hardware Control Mode.......................................................................................126
4.5.3
Power-Down Mode..............................................................................................127
4.5.3.1
Global (Hardware) Power Down..........................................................128
4.5.3.2
Port (Software) Power Down ...............................................................128
4.5.4
Reset ...................................................................................................................128
4.5.5
Hardware Configuration Settings.........................................................................129
Link Establishment............................................................................................................129
4.6.1
Auto-Negotiation..................................................................................................129
4.6.1.1
Base Page Exchange ..........................................................................129
4.6.1.2
Manual Next Page Exchange ..............................................................130
4.6.1.3
Controlling Auto-Negotiation................................................................130
4.6.1.4
Link Criteria..........................................................................................130
4.6.1.5
Parallel Detection.................................................................................131
4.6.1.6
Reliable Link Establishment While Auto MDI/MDIX is
Enabled in Forced Speed Mode ..........................................................131
Serial MII Operation..........................................................................................................132
4.7.1
SMII Reference Clock..........................................................................................135
4.7.2
TxSYNC Pulse (SMII/SS-SMII)............................................................................135
4.7.3
Transmit Data Stream..........................................................................................135
4.7.3.1
Transmit Enable...................................................................................135
4.7.3.2
Transmit Error......................................................................................135
4.7.4
Receive Data Stream...........................................................................................136
4.7.4.1
Carrier Sense.......................................................................................136
4.7.4.2
Receive Data Valid ..............................................................................136
4.7.4.3
Receive Error.......................................................................................136
4.7.4.4
Receive Status Encoding.....................................................................136
4.7.5
Collision...............................................................................................................136
4.7.6
Source Synchronous-Serial Media Independent Interface..................................137
RMII Operation .................................................................................................................141
4.8.1
RMII Reference Clock..........................................................................................141
4.8.2
Transmit Enable...................................................................................................142
4.8.3
Carrier Sense & Data Valid..................................................................................142
4.8.4
Receive Error.......................................................................................................142
4.8.5
Out-of-Band Signaling .........................................................................................142
4.8.6
4B/5B Coding Operations....................................................................................142
100 Mbps Operation.........................................................................................................145
MDIO Management Interface ..............................................................................121
MII Sectionalization..............................................................................................123
MII Interrupts........................................................................................................123
4.4
4.5
4.6
4.7
4.8
4.9
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DJIXPLAD0QE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXPLAD0QE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXPLAD0SE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXPLAD0SE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXPLCD0QE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DJIXPLAD0QE000 | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXPLAD0QE001 | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXPLAD0SE000 | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXPLAD0SE001 | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXPLCD0QE000 | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。