- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376725 > DJLXT972MBEA4 (Intel Corp.) Single-Port 10/100 Mbps PHY Transceiver PDF資料下載
參數(shù)資料
| 型號： | DJLXT972MBEA4 |
| 廠商： | Intel Corp. |
| 英文描述： | Single-Port 10/100 Mbps PHY Transceiver |
| 中文描述： | 單端口10/100 Mbps的物理層收發(fā)器 |
| 文件頁數(shù)： | 81/92頁 |
| 文件大?。?/td> | 666K |
| 代理商： | DJLXT972MBEA4 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁當(dāng)前第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁
Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
81
Table 47
lists auto-negotiation expansion bits.
Table 47. Auto-Negotiation Expansion - Address 6, Hex 6
Bit
Name
Description
Type
1
Default
6.15:6
Reserved
Ignore when read.
RO
0
6.5
Base Page
This bit indicates the status of the auto-negotiation
variable base page. It flags synchronization with the
auto-negotiation state diagram, allowing detection of
interrupted links. This bit is used only if Register bit
16.1 (that is, Alternate NP feature) is set.
0 = Base page = False (base page not received)
1 = Base page = True (base page received)
RO/LH
0
6.4
Parallel
Detection Fault
0 = Parallel detection fault has not occurred.
1 = Parallel detection fault has occurred.
RO/LH
0
6.3
Link Partner
Next Page Able
0 = Link partner is not next page able.
1 = Link partner is next page able.
RO
0
6.2
Next Page Able
0 = Local device is not next page able.
1 = Local device is next page able.
RO
1
6.1
Page Received
This bit is cleared on Read. If Register bit 16.1 is set,
the Page Received bit is also cleared when either
mr_page_rx = false or transmit_disable = true.
1 = Indicates a new page is received and the received
code word is loaded into Register 5 (Base Pages)
or Register 8 (Next Pages) as specified in Clause
28 of IEEE 802.3.
RO/LH
0
6.0
Link Partner A/N
Able
0 = Link partner is not auto-negotiation able.
1 = Link partner is auto-negotiation able.
RO
0
1. RO = Read Only LH = Latching High
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DJLXT972MCAA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MCCA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MCEA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MEAA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MECA4 | Single-Port 10/100 Mbps PHY Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DJLXT972MCAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MCCA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MCEA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MEAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MECA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。