參數(shù)資料
型號: DJLXT972MKEA4
廠商: Intel Corp.
英文描述: Single-Port 10/100 Mbps PHY Transceiver
中文描述: 單端口10/100 Mbps的物理層收發(fā)器
文件頁數(shù): 75/92頁
文件大?。?/td> 666K
代理商: DJLXT972MKEA4
Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
75
8.0
Register Definitions - IEEE Base Registers
This chapter includes definitions for the IEEE base registers used by the LXT972M Transceiver.
Chapter 9.0, “Register Definitions - Product-Specific Registers”
includes definitions of additional
product-specific LXT972M Transceiver registers, which are defined in accordance with the IEEE
802.3 standard for adding unique device functions.
The LXT972M Transceiver register set has multiple 16-bit registers.
Table 40
is a register set listing of the IEEE base registers.
Table 41
through
Table 49
provide bit descriptions of the base registers (address 0 through 8),
which are defined in accordance with the “Reconciliation Sublayer and Media Independent
Interface” and “Physical Layer Link Signaling for 10/100 Mbps Auto-Negotiation” sections of
the IEEE 802.3 standard.
Table 40. Register Set for IEEE Base Registers
Address
Register Name
Bit Assignments
0
Control Register
See
Table 41
1
Status Register #1
See
Table 42.
2
PHY Identification Register 1
See
Table 43.
3
PHY Identification Register 2
See
Table 44.
4
Auto-Negotiation Advertisement Register
See
Table 45
5
Auto-Negotiation Link Partner Base Page Ability Register
See
Table 46.
6
Auto-Negotiation Expansion Register
See
Table 47.
7
Auto-Negotiation Next Page Transmit Register
See
Table 48.
8
Auto-Negotiation Link Partner Next Page Receive Register
See
Table 49.
9
1000BASE-T/100BASE-T2 Control Register
Not Implemented
10
1000BASE-T/100BASE-T2 Status Register
Not Implemented
11 to 14
Reserved
Not Implemented
15
Extended Status Register
Not Implemented
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