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參數(shù)資料
| 型號(hào)： | DJLXTPED0SE000 |
| 廠商： | Intel Corp. |
| 英文描述： | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| 中文描述： | 先進(jìn)的8端口10/100 Mbps的物理層收發(fā)器 |
| 文件頁(yè)數(shù)： | 126/226頁(yè) |
| 文件大?。?/td> | 1575K |
| 代理商： | DJLXTPED0SE000 |
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
128
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Note:
Intel recommends that a minimum recovery time be allowed after bringing up a port from software
or hardware power-down or link hold-off modes. The recovery times are specified in
Table 80,
“Intel LXT9785/LXT9785E Power-Up Timing Parameters” on page 198
4.5.3.1
Global (Hardware) Power Down
The global power-down mode is controlled by the PWRDWN pin. When PWRDWN is High, the
following conditions are true:
All LXT9785/LXT9785E ports and the clock are shut down.
All outputs are three-stated.
All weak pad pull-up and pull-down resistors are disabled.
The MDIO registers are not accessible.
Configuration pins are read upon release of the PWRDWN pin, and registers are loaded with
the current values of the hardware configuration pins.
4.5.3.2
Port (Software) Power Down
Individual port power-down control is provided by Register bit 0.11 in the respective port Control
Registers (refer to
Table 83, “Control Register (Address 0)” on page 200
). During individual port
power-down, the following conditions are true:
The individual port is shut down.
The MDIO registers remain accessible.
Pull-up and pull-down resisters are not affected and the outputs are not three-stated.
The register remains unchanged.
4.5.4
Reset
The LXT9785/LXT9785E provides both hardware and software resets. Configuration control of
Auto-Negotiation, speed, and duplex mode selection is handled differently for each. During a
hardware reset, settings for bits 0.13, 0.12, 0.8, and 4.8:5 are read in from the pins (refer to
Table 42, “Intel LXT9785/9785E Global Hardware Configuration Settings” on page 129
for pin
settings, and
Table 83, “Control Register (Address 0)” on page 200
and
Table 87, “Auto-
Negotiation Advertisement Register (Address 4)” on page 204
for register bit definitions).
During a software reset (Register bit 0.15 = 1), the bit settings are not re-read from the pins and
revert back to the values that were read in during the last hardware reset. Any changes to pin values
from the last hardware reset are not detected during a software reset.
During a hardware reset, register information is unavailable for 1 ms after de-assertion of the reset.
All MII interface pins are disabled during a hardware reset and released to the bus on de-assertion
of reset.
During a software reset (0.15 = 1) the registers are available for reading. The reset bit should be
polled to see when the part has completed reset (0.15 = 0). Pull up and pull down resisters are not
affected.
相關(guān)PDF資料 |
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| DJLXTPED0SE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
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| DJIXEPAD0SE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEPAD0SE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DJLXTPED0SE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
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