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參數(shù)資料
| 型號(hào)： | DK86060-3 |
| 廠商： | Fujitsu Limited |
| 元件分類： | DAC |
| 英文描述： | 16-Bit Interpolating Digital to Analog Converter |
| 中文描述： | 16位插數(shù)模轉(zhuǎn)換器 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 105K |
| 代理商： | DK86060-3 |
June 2000
Version 1.2
FME/MS/SFDAC1/FL_1/4270
MB86060
16-Bit Interpolating Digital to Analog Converter
Copyright 2000 Fujitsu Microelectronics Europe GmbH
Page 3 of 6
Segment Shuffling
The DAC core incorporates a proprietary segment shuffling capability which is provided to further improve
linearity, and hence improve SFDR. This feature reduces any signal level dependent effects on linearity as
the same code can be generated by the same number of MSB cells but taken from any quarter of the MSB
segments. Segment shuffling can be selected to operate every 4, 8 or 16 updates of the DAC output using
a random shuffle sequence between the four segments. Most performance improvement will be observed
when the device is used in one of the interpolating modes. The effect of segment shuffling is to produce a
spread noise spectrum, raising the overall noise
floor, but reducing the distortion. For minimum
distortion when generating low frequency
signals, it is recommended that the shuffling
clock rate is no more than 25MHz (DAC Rate /
Segment Shuffling setting). However, low
shuffle clock rates give reduced spreading out of
distortion components.
75
Noise Shaping
Second order noise shaping can be applied to
interpolated data prior to being passed to the
DAC core. When enabled this provides an
additional reduction in quantisation noise to that
gained through the use of interpolation filtering.
For the x4 interpolation mode this improvement
will be 16dB, equivalent to 2.7 bits.
Clock
The MB86060 incorporates a clock multiplier to generate the required internal x1, x2 and x4 clock signals
from an external reference. The clock multiplier is based on a delay-lock-loop whose delay is adjusted by
a charge pump controlled by a phase detector. A ‘Lock’ indicator is provided so that the system can monitor
the multiplier’s condition. For systems where a high frequency clock is available, or the lowest possible jitter
is required, then the clock multiplier may be disabled and the external clock used directly.
Interpolating Filters
The integration of interpolating filters provides a number of benefits to the system implementation. In
general, improved performance can be gained by using a higher DAC conversion rate effectively providing
a higher level of oversampling from the generated signal. For the designer, the problem with this approach
is generating the required high speed digital data, especially when considering high performance wide-
band designs with up to 50MHz of signal. Integrating this processing on-chip with the DAC alleviates this
problem.
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65
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80
85
90
95
0
10
20
30
40
Generated Frequency
(MHz)
S
(
50MSa/s Input Data Rate
x4 Mode, 200MSa/s DAC Rate
Noise Shaper On, Dither Off
Amplitude = -1dBFS
Shuffle On
Shuffle Off
Single Tone SFDR Performance
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