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參數(shù)資料
| 型號(hào)： | DK86064-1-SMA |
| 廠商： | Fujitsu Semiconductor America Inc |
| 文件頁(yè)數(shù)： | 2/4頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEV DUAL 14BIT MB86064 SMA |
| 特色產(chǎn)品： | High Performance Data Converters |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 附件類(lèi)型： | 接口板 |
| 適用于相關(guān)產(chǎn)品： | MB86064，MB86065，DK86064-2，DK86065-2 |
| 產(chǎn)品目錄頁(yè)面： | 1261 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | 865-1011-ND - KIT EVAL 16BIT DAC FOR MB86065 865-1010-ND - KIT DEB DUAL 14BIT DAC MB86064 865-1007-ND - DAC 14BIT 1GSA/S DUAL 12-EFBGA |
| 其它名稱(chēng)： | 865-1012 |
January 2008 Version 2.1
FME/MS/DAC80/FL_2/5084
DK86064-2 Dual 14-bit 1GSa/s DAC Development Kit
Page 2 of 4
Production
Copyright 2004-2008 Fujitsu Microelectronics Europe GmbH
Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before
ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.
Essential Equipment
Apart from the power supplies, the minimum
equipment vital to conducting an evaluation of
the MB86064 is a high quality RF clock and
spectrum analyser. The phase & spurious
performance of the clock should be such as to
not limit the DAC performance (e.g. HP8664A).
However,
performance
of
even
the
best
spectrum analysers available is inferior to that of
the
converter.
To
overcome
this,
filtering
techniques and careful attention to analyser
settings, e.g. RF Attenuation, is essential during
the course of the evaluation.
Driving the DAC
As with any DAC evaluation an appropriate test
vector stimulus is required. Unfortunately at data
rates above 300MSa/s this requires digital
pattern generation capabilities beyond most
standard
test
equipment.
The
DK86064-2
Development Kit has been designed to help
overcome this difficulty in a number of ways.
Initially,
unmodulated
or
pseudo-modulated
single
and
multi-tone/carrier
tests
can
be
conducted using waveforms downloaded to the
on-chip memories.
Test waveforms are easily loaded into the
memories using the PC software and USB
programming cable supplied. Even if high speed
digital pattern generating equipment is available,
initial testing using the waveform memories
serves as a useful setup check.
Pattern
generators
can be connected to
the evaluation board
using either the on-
board 2-row 0.1" data
headers, or via ribbon
cables to the optional
SMA adaptors. When
using the 0.1" data
headers it is assumed
that a custom wiring
harness
will
be
required. This would
be made according to
the
connector
type
and
pinout
of
the
generator’s
output.
The
optional
SMA
adaptors provide a convenient conversion from
SMA to the evaluation board’s 0.1" headers. This
alleviates the simultaneous removal of 28 SMAs
(14-bit differential LVDS) when required to be
disconnected. One advantage of this is the ability
to easily swap the data generator between DAC
data ports if insufficient channels are available to
drive both ports simultaneously.
Rather
than
using
general
purpose
test
equipment, customers may wish to use the
evaluation board to construct a platform more
representative of their end application. This
might,
for
example,
involve
an
FPGA
to
implement a variety of pre-processing and/or
waveform generation functions. At the simplest
level, a setup similar to that described for the
digital pattern generator could be used, where a
custom wiring harness interfaces a standard or
existing FPGA platform to the DAC evaluation
board. Control of the DAC from the PC software
can be maintained to minimise effort to get up
and running.
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