參數(shù)資料
型號(hào)： DM6580L
廠商： Electronic Theatre Controls, Inc.
英文描述： V.90 Intergrated Data/Fax/Voice/Speakephone Modem Device Single Chip with Memory Built in
中文描述： .90綜合數(shù)據(jù)/傳真/語(yǔ)音/ Speakephone調(diào)制解調(diào)器設(shè)備的單芯片，具有內(nèi)置的記憶
文件頁(yè)數(shù)： 8/43頁(yè)
文件大小： 292K
代理商： DM6580L
DM562P
V.90 Integrated Data/ Fax/Voice/Speakerphone
Modem Device Single Chip with Memory Built in
8
Preliminary
Version: DM562P-DS-P02
February 28, 2001
For the accesses to the configuration address space, the device select
decoding is done externally and is signaled via this pin. This signal is
asserted high during configuration read and write access.
PCI Bus Command/Byte Enable
During the address phase, these signals define the bus command or
the type of the bus transaction that will take place.
During the data phase, these pins indicate which byte lanes contain
valid data. C/BE0# applies to bit7~0 and C/BE3# applies to bit 31~24.
PCI Cycle Frame
This signal is driven low by the master to indicate the beginning and
duration of a bus transaction. It is deasserted when the transaction is
in its final phase.
PCI Initiator Ready
This signal is driven low when the master is ready to complete the
current data phase of the transaction. A data phase is completed on
any clock both IRDY# and TRDY# are sampled asserted.
PCI Target Ready
This signal is driven low when the target is ready to complete the
current data phase of the transaction. During a read, it indicates that
the valid data is asserted. During write, it indicates that the target
prepares to accept data.
PCI Device Select
DM6585 asserts the signal low when it recognizes its target address
after FRAME# is asserted.
PCI Stop
This signal is asserted low by the target device to request the master
device to stop the current transaction.
PCI Parity Error
DM6585 will assert this signal low to indicate a parity error on any
incoming data.
PCI System Error
This signal is asserted low when an address parity is detected with
PCICS bit31 enabled. The system error asserts two clock cycles after
the address if an address parity error is detected.
PCI Parity
This signal indicates even parity across AD0~AD31 and
C/BE0#~C/BE3# including the PAR pin. It is stable and valid one clock
after the address phase.
Reset:
An active low signal used to reset the DM6588.
+3.3V Auxiliary Power Supply
Ring Signal Input for Auxiliary Power
Auxiliary Ground
8
18
28
44
C/BE3#
C/BE2#
C/BE1#
C/BE0#
I
19
FRAME#
I
21
IRDY#
I
22
TRDY#
I/O
23
DEVSEL#
I/O
24
STOP#
I/O
25
PERR#
I/O
26
SERR#
O
27
PAR
I/O
36
RST#
I
74
76
77
VCC_AUX
RIN
GND_AUX
P
I
P
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