參數(shù)資料
型號: DM7490AN
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Decade and Binary Counters
中文描述: TTL/H/L SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, PDIP14
封裝: 0.300 INCH, PLASTIC, MS-001, DIP-14
文件頁數(shù): 4/5頁
文件大?。?/td> 47K
代理商: DM7490AN
www.fairchildsemi.com
4
D
AC Switching Characteristics
at V
CC
=
5V and T
A
=
25
°
C
Symbol
Parameter
From (Input)
R
L
=
400
, C
L
=
15 pF
Min
32
16
Units
To (Output)
A to Q
A
B to Q
B
Max
f
MAX
Maximum Clock
Frequency
Propagation Delay Time
MHz
t
PLH
A to Q
A
16
ns
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
t
PHL
A to Q
A
18
ns
t
PLH
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
A to Q
D
48
ns
t
PHL
A to Q
D
50
ns
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
t
PLH
B to Q
B
16
ns
t
PHL
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
B to Q
B
21
ns
t
PLH
B to Q
C
32
ns
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
t
PHL
B to Q
C
35
ns
t
PLH
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
B to Q
D
32
ns
t
PHL
B to Q
D
35
ns
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
t
PLH
SET-9 to Q
A
, Q
D
30
ns
t
PHL
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
SET-9 to Q
B
, Q
C
40
ns
t
PHL
SET-0
40
ns
HIGH-to-LOW Level Output
Any Q
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