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參數(shù)資料
| 型號： | DM74ALS74 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear |
| 中文描述： | 雙D上升沿觸發(fā)器的預置和清除 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 68K |
| 代理商： | DM74ALS74 |
2000 Fairchild Semiconductor Corporation
DS006109
www.fairchildsemi.com
September 1986
Revised February 2000
D
DM74ALS74A
Dual D Positive-Edge-Triggered Flip-Flop
with Preset and Clear
General Description
The DM74ALS74A contains two independent positive
edge-triggered flip-flops. Each flip-flop has individual D,
clock, clear and preset inputs, and also complementary Q
and Q outputs.
Information at input D is transferred to the Q output on the
positive going edge of the clock pulse. Clock triggering
occurs at a voltage level of the clock pulse and is not
directly related to the transition time of the positive going
pulse. When the clock input is at either the HIGH or LOW
level, the D input signal has no effect.
Asynchronous preset and clear inputs will set or clear Q
output respectively upon the application of low level signal.
Features
I
Switching specifications at 50 pF
I
Switching specifications guaranteed over full tempera-
ture and V
CC
range
I
Advanced oxide-isolated, ion-implanted Schottky TTL
process
I
Functionally and pin-for-pin compatible with Schottky
and LS TTL counterpart
I
Improved AC performance over LS74 at approximately
half the power
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
L
=
LOW State
H
=
HIGH State
X
=
Don't Care
↑
=
Positive Edge Transition
Q
0
=
Previous Condition of Q
Note 1:
This condition is nonstable; it will not persist when preset and clear
inputs return to their inactive (HIGH) level. The output levels in this condi-
tion are not guaranteed to meet the V
OH
specification.
Order Number
DM74ALS74AM
DM74ALS74ASJ
DM74ALS74AN
Package Number Package Description
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs
Outputs
PR
L
H
L
H
H
H
CLR
H
L
L
H
H
H
CLK
X
X
X
↑
↑
L
D
X
X
X
H
L
X
Q
H
L
Q
L
H
H (Note 1)
H
L
Q
0
H (Note 1)
L
H
Q
0
相關PDF資料 |
PDF描述 |
|---|---|
| DM74ALS74AM | Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear |
| DM74ALS86 | 10-Bit Buffer/Driver With 3-State Outputs 24-TSSOP -40 to 85 |
| DM74ALS86M | Quad 2-Input Exclusive-OR Gate |
| DM74ALS86N | Quad 2-Input Exclusive-OR Gate |
| DM74ALS86MX | Quad 2-input Exclusive OR (XOR) Gate |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DM74ALS74AM | 功能描述:觸發(fā)器 Dual D Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| DM74ALS74AM_Q | 功能描述:觸發(fā)器 Dual D Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| DM74ALS74AMX | 功能描述:觸發(fā)器 Dual D Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| DM74ALS74AN | 功能描述:觸發(fā)器 Dual D Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| DM74ALS74AN_Q | 功能描述:觸發(fā)器 Dual D Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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