參數(shù)資料
型號: DM74AS651WM
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: 9-Bit Bus Transceiver With 3-State Outputs 24-TVSOP -40 to 85
中文描述: AS SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO24
封裝: 0.300 INCH, MS-013, SOIC-24
文件頁數(shù): 5/8頁
文件大小: 71K
代理商: DM74AS651WM
5
www.fairchildsemi.com
D
DM74AS651 Switching Characteristics
Note 4:
These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
Symbol
f
MAX
t
PLH
Parameter
Conditions
From
To
Min
90
Max
Units
MHz
Maximum Clock Frequency
Propagation Delay Time
V
CC
=
4.5V to 5.5V
R
1
=
R
2
=
500
C
L
=
50 pF
2
8.5
ns
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
CBA or CAB
A or B
t
PHL
2
9
ns
t
PLH
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
2
8
ns
A or B
B or A
t
PHL
1
7
ns
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
t
PLH
2
11
ns
SBA or SAB
A or B
t
PHL
Propagation Delay Time
HIGH-to-LOW Level Output
Output Enable Time
(Note 4)
2
9
ns
t
PZH
2
10
ns
to HIGH Level Output
Output Enable Time
to LOW Level Output
t
PZL
3
16
ns
Enable GBA
A
t
PHZ
Output Disable Time
from HIGH Level Output
Output Disable Time
2
9
ns
t
PLZ
2
9
ns
from LOW Level Output
Output Disable Time
to HIGH Level Output
t
PZH
3
11
ns
t
PZL
Output Disable Time
to LOW Level Output
Output Disable Time
3
16
ns
Enable GAB
B
t
PHZ
2
10
ns
from HIGH Level Output
Output Disable Time
t
PLZ
2
11
ns
from LOW Level Output
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