參數(shù)資料
型號(hào): DM74AS652WM
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類(lèi): 通用總線功能
英文描述: Octal Bus Transceiver and Register
中文描述: AS SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24
封裝: 0.300 INCH, MS-013, SOIC-24
文件頁(yè)數(shù): 2/8頁(yè)
文件大小: 71K
代理商: DM74AS652WM
www.fairchildsemi.com
2
D
Connection Diagram
Function Table
H
=
HIGH Level
L
=
LOW Level
X
=
Irrelevant
=
LOW-to-HIGH Transition
Note 1:
The data output functions may be enabled or disabled by various signals at the GAB and GBA inputs. Data input functions are always enabled,
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
Note 2:
If the select control is LOW, the clocks can occur simultaneously. If the select control is HIGH, the clocks must be staggered in order to load both
registers.
INPUTS
DATA I/O (Note 1)
OPERATION OR FUNCTION
GAB GBA
CAB
CBA
SAB
SBA
A1
THRU
A8
B1
THRU
B8
DM74AS651
DM74AS652
L
L
H
H
H or L H or L
X
X
X
X
Input
Input
Isolation
Store A and B Data
Isolation
Store A and B Data
L
L
X
X
X
L
Output
Input
Real Time B Data to A
Bus
Stored B Data to A Bus
Real Time B Data to A
Bus
Stored B Data to A Bus
L
L
X
H or L
X
H
H
H
X
X
L
X
Input
Output
Real Time A Data to B
Bus
Stored A Data to B Bus
Real Time A Data to B
Bus
Stored A Data to B Bus
H
H
H or L
X
H
X
H
L
H or L H or L
H
H
Output
Output
Stored A Data to B Bus
& Stored B Data to A Bus & Stored B Data to A Bus
Store A, Hold B
Stored A Data to B Bus
X
H
H or L
X
X
Input
Unspecified
(Note 1)
Output
Store A, Hold B
H
H
X
(Note
2)
X
X
Input
Store A in both registers
Store A in both registers
L
X
H or L
X
Unspecified
(Note 1)
Output
Input
Hold A, Store B
Hold A, Store B
L
L
X
X
(Note
2)
Input
Store B in both registers
Store B in both registers
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