- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376786 > DM74LS109A (Fairchild Semiconductor Corporation) Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs(雙正邊緣觸發(fā)的J-K觸發(fā)器（帶預(yù)置、清除端、互補(bǔ)輸出）) PDF資料下載
參數(shù)資料
| 型號(hào)： | DM74LS109A |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs(雙正邊緣觸發(fā)的J-K觸發(fā)器（帶預(yù)置、清除端、互補(bǔ)輸出）) |
| 中文描述： | 雙上升沿觸發(fā)JK觸發(fā)器的預(yù)置，清除，互補(bǔ)輸出（雙正邊緣觸發(fā)的JK觸發(fā)器（帶預(yù)置，清除端，互補(bǔ)輸出）） |
| 文件頁(yè)數(shù)： | 1/5頁(yè) |
| 文件大?。?/td> | 52K |
| 代理商： | DM74LS109A |
2000 Fairchild Semiconductor Corporation
DS006368
www.fairchildsemi.com
June 1986
Revised March 2000
D
DM74LS109A
Dual Positive-Edge-Triggered J-K Flip-Flop with
Preset, Clear, and Complementary Outputs
General Description
This device contains two independent positive-edge-trig-
gered J-K flip-flops with complementary outputs. The J and
K data is accepted by the flip-flop on the rising edge of the
clock pulse. The triggering occurs at a voltage level and is
not directly related to the transition time of the rising edge
of the clock. The data on the J and K inputs may be
changed while the clock is HIGH or LOW as long as setup
and hold times are not violated. A low logic level on the
preset or clear inputs will set or reset the outputs regard-
less of the logic levels of the other inputs.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
H
=
HIGH Logic Level
L
=
LOW Logic Level
X
=
Either LOW or HIGH Logic Level
↑
=
Rising Edge of Pulse
Q
0
=
The output logic level of Q before the indicated input conditions were
established.
Toggle
=
Each output changes to the complement of its previous level on
each active transition of the clock pulse.
Note 1:
This configuration is nonstable; that is, it will not persist when pre-
set and/or clear inputs return to their inactive (HIGH) state.
Order Number
DM74LS109AM
DM74LS109AN
Package Number
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs
Outputs
PR
L
H
L
H
H
CLR
H
L
L
H
H
CLK
X
X
X
↑
↑
↑
↑
L
J
X
X
X
L
H
K
X
X
X
L
L
Q
H
L
Q
L
H
H (Note 1) H (Note 1)
L
Toggle
H
H
H
H
H
H
H
L
H
X
H
H
X
Q
0
H
Q
0
Q
0
L
Q
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DM74LS109 | Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs |
| DM74LS109AM | Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs |
| DM74LS109AN | Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs |
| DM74LS109AMX | J-K-Type Flip-Flop |
| DM74LS10M | Triple 3-Input NAND Gate |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM74LS109A WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| DM74LS109AM | 功能描述:觸發(fā)器 Dl J-K Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| DM74LS109AMX | 功能描述:觸發(fā)器 Dl J-K Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| DM74LS109AN | 功能描述:觸發(fā)器 Dl J-K Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| DM74LS109AN83 | 制造商:National Semiconductor 功能描述:74LS109N |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。