參數(shù)資料
型號: DM74LS390N
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Dual 4-Bit Decade Counter
中文描述: LS SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, PDIP16
封裝: 0.300 INCH, PLASTIC, MS-001, DIP-16
文件頁數(shù): 1/6頁
文件大小: 58K
代理商: DM74LS390N
2000 Fairchild Semiconductor Corporation
DS006433
www.fairchildsemi.com
August 1986
Revised March 2000
D
DM74LS390
Dual 4-Bit Decade Counter
General Description
Each of these monolithic circuits contains eight master-
slave flip-flops and additional gating to implement two indi-
vidual four-bit counters in a single package. The
DM74LS390 incorporates dual divide-by-two and divide-
by-five counters, which can be used to implement cycle
lengths equal to any whole and/or cumulative multiples of 2
and/or 5 up to divide-by-100. When connected as a bi-qui-
nary counter, the separate divide-by-two circuit can be
used to provide symmetry (a square wave) at the final out-
put stage. The DM74LS390 has parallel outputs from each
counter stage so that any submultiple of the input count fre-
quency is available for system-timing signals.
Features
I
Dual version of the popular DM74LS90
I
DM74LS390...individual clocks for A and B flip-flops
provide dual
÷
2 and
÷
5 counters
I
Direct clear for each 4-bit counter
I
Dual 4-bit version can significantly improve system den-
sities by reducing counter package count by 50%
I
Typical maximum count frequency...35 MHz
I
Buffered outputs reduce possibility of collector commu-
tation
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number
DM74LS390M
DM74LS390N
Package Number
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
相關(guān)PDF資料
PDF描述
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